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Rev 1295 Rev 1611
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#
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#
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# Copyright (C) 2005 Jakub Jermar
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# Copyright (C) 2005 Jakub Jermar
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# All rights reserved.
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# All rights reserved.
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#
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#
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# Redistribution and use in source and binary forms, with or without
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions
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# modification, are permitted provided that the following conditions
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# are met:
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# are met:
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#
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#
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# - Redistributions of source code must retain the above copyright
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# - Redistributions of source code must retain the above copyright
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#   notice, this list of conditions and the following disclaimer.
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#   notice, this list of conditions and the following disclaimer.
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# - Redistributions in binary form must reproduce the above copyright
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# - Redistributions in binary form must reproduce the above copyright
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#   notice, this list of conditions and the following disclaimer in the
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#   notice, this list of conditions and the following disclaimer in the
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#   documentation and/or other materials provided with the distribution.
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#   documentation and/or other materials provided with the distribution.
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# - The name of the author may not be used to endorse or promote products
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# - The name of the author may not be used to endorse or promote products
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#   derived from this software without specific prior written permission.
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#   derived from this software without specific prior written permission.
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#
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#
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# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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#
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#include <arch/register.h>
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#include <arch/register.h>
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.text
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.text
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/** Copy memory from/to userspace.
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/** Copy memory from/to userspace.
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 *
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 *
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 * This memcpy() has been taken from the assembler output of
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 * This memcpy() has been taken from the assembler output of
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 * the generic _memcpy() and modified to have the failover part.
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 * the generic _memcpy() and modified to have the failover part.
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 *
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 *
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 * @param in0 Destination address.
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 * @param in0 Destination address.
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 * @param in1 Source address.
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 * @param in1 Source address.
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 * @param in2 Number of byte to copy.
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 * @param in2 Number of byte to copy.
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 */
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 */
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.global memcpy
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.global memcpy
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.global memcpy_from_uspace
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.global memcpy_from_uspace
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.global memcpy_to_uspace
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.global memcpy_to_uspace
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.global memcpy_from_uspace_failover_address
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.global memcpy_from_uspace_failover_address
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.global memcpy_to_uspace_failover_address
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.global memcpy_to_uspace_failover_address
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memcpy:
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memcpy:
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memcpy_from_uspace:
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memcpy_from_uspace:
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memcpy_to_uspace:
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memcpy_to_uspace:
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	alloc loc0 = ar.pfs, 3, 1, 0, 0
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	alloc loc0 = ar.pfs, 3, 1, 0, 0
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 51 
 
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	shr.u r18 = in2, 3
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	adds r14 = 7, in1
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	mov r8 = in1 ;;			/* prepare to return in1 on success */
 - 
 
54 
	cmp.ne p6, p7 = 0, r18	;;
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	mov r2 = ar.lc
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(p7)	mov r17 = r0
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	mov r8 = in1 ;;
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(p7)	br.cond.dptk 1f ;;
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	and r14 = -8, r14 ;;
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	mov r16 = r0
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	cmp.ne p6, p7 = r14, in1
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	mov r17 = r0 ;;
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(p7)	br.cond.dpnt 3f	;;
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 - 
 
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0:
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0:
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	shladd r14 = r17, 3, r0
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	cmp.ne p6, p7 = 0, in2
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	adds r16 = 1, r16 ;;
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(p7)	br.cond.dpnt 2f	;;
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	add r15 = r14, r8
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(p6)	adds r14 = -1, in2
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	sxt4 r17 = r16
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(p6)	mov r16 = r0
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	add r14 = r14, in0 ;;
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(p6)	mov r17 = r0 ;;
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	ld8 r15 = [r15]
 - 
 
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	cmp.gtu p6, p7 = r18, r17 ;;
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	st8 [r14] = r15
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(p6)	mov ar.lc = r14
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(p6)	br.cond.dptk 0b
 - 
 
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 - 
 
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1:
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1:
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	and in2 = 7, in2 ;;
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	add r14 = r16, r8
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	cmp.eq p6, p7 = 0, in2 ;;
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	add r15 = r16, in0
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(p6)	mov ar.pfs = loc0
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(p6)	br.ret.dptk.many rp
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	shladd r14 = r17, 3, r0
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	adds r17 = 1, r17 ;;
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	mov r16 = r0
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	ld1 r14 = [r14]
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	mov r17 = r0 ;;
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	mov r16 = r17 ;;
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	add in0 = in0, r14
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	st1 [r15] = r14
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	add r18 = r8, r14 ;;
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	br.cloop.sptk.few 1b ;;
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 - 
 
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2:
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2:
- 
 
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	mov ar.lc = r2
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- 
 
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	mov ar.pfs = loc0
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	br.ret.sptk.many rp
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3:
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	adds r14 = 7, in0 ;;
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	and r14 = -8, r14 ;;
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	cmp.eq p6, p7 = r14, in0
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(p7)	br.cond.dptk 0b
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	shr.u r18 = in2, 3 ;;
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	cmp.ne p6, p7 = 0, r18
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(p7)	br.cond.dpnt 5f	;;
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(p6)	adds r14 = -1, r18
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(p6)	mov r16 = r0
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(p6)	mov r17 = r0 ;;
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(p6)	mov ar.lc = r14
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4:
- 
 
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	shladd r14 = r16, 3, r0
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	adds r16 = 1, r17 ;;
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	add r15 = r8, r14
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	add r14 = r16, r18
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	add r14 = in0, r14
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	mov r17 = r16 ;;
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	ld8 r15 = [r15] ;;
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	st8 [r14] = r15
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	br.cloop.sptk.few 4b
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5:
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	and r15 = 7, in2
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	shladd r14 = r18, 3, r0
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	mov r16 = r0
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	mov r18 = r0 ;;
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	cmp.eq p6, p7 = 0, r15
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	add in0 = r14, in0
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	adds r17 = 1, r17
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	adds r15 = -1, r15
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	add r17 = r14, r8
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(p6)	br.cond.dpnt 2b	;;
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	mov ar.lc = r15
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6:
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	add r14 = r16, r17
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	add r15 = r16, in0
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	add r15 = in0, r16 ;;
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	adds r16 = 1, r18 ;;
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	ld1 r14 = [r14]
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	ld1 r14 = [r14]
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	sxt4 r16 = r17	;;
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	mov r18 = r16 ;;
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	st1 [r15] = r14
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	st1 [r15] = r14
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	cmp.gtu p6, p7 = in2, r16
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	br.cloop.sptk.few 6b ;;
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(p6)	br.cond.dptk 2b
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	mov ar.lc = r2
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	mov ar.pfs = loc0
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	mov ar.pfs = loc0
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	br.ret.sptk.many rp
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	br.ret.sptk.many rp
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memcpy_from_uspace_failover_address:
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memcpy_from_uspace_failover_address:
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memcpy_to_uspace_failover_address:
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memcpy_to_uspace_failover_address:
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	mov r8 = r0			/* return 0 on failure */
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	mov r8 = r0			/* return 0 on failure */
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	mov ar.pfs = loc0
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	mov ar.pfs = loc0
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	br.ret.sptk.many rp
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	br.ret.sptk.many rp
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.global memsetb
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.global memsetb
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memsetb:
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memsetb:
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	br _memsetb
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	br _memsetb
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.global cpu_halt
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.global cpu_halt
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cpu_halt:
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cpu_halt:
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	br cpu_halt
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	br cpu_halt
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.global panic_printf
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.global panic_printf
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panic_printf:
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panic_printf:
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	{
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	{
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		br.call.sptk.many b0=printf
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		br.call.sptk.many b0=printf
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	}
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	}
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	br halt
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	br halt
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/** Switch to userspace - low level code.
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/** Switch to userspace - low level code.
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 *
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 *
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 * @param in0 Userspace entry point address.
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 * @param in0 Userspace entry point address.
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 * @param in1 Userspace stack pointer address.
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 * @param in1 Userspace stack pointer address.
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 * @param in2 Userspace register stack pointer address.
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 * @param in2 Userspace register stack pointer address.
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 * @param in3 Userspace address of thread uspace_arg_t structure.
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 * @param in3 Userspace address of thread uspace_arg_t structure.
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 * @param in4 Value to be stored in IPSR.
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 * @param in4 Value to be stored in IPSR.
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 * @param in5 Value to be stored in RSC.
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 * @param in5 Value to be stored in RSC.
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 */
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 */
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.global switch_to_userspace
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.global switch_to_userspace
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switch_to_userspace:
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switch_to_userspace:
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	alloc loc0 = ar.pfs, 6, 3, 0, 0
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	alloc loc0 = ar.pfs, 6, 3, 0, 0
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	rsm (PSR_IC_MASK | PSR_I_MASK)		/* disable interruption collection and interrupts */
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	rsm (PSR_IC_MASK | PSR_I_MASK)		/* disable interruption collection and interrupts */
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	srlz.d ;;
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	srlz.d ;;
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	srlz.i ;;
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	srlz.i ;;
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	mov cr.ipsr = in4
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	mov cr.ipsr = in4
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	mov cr.iip = in0
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	mov cr.iip = in0
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	mov r12 = in1
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	mov r12 = in1
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	xor r1 = r1, r1
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	xor r1 = r1, r1
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165
138 
	mov loc1 = cr.ifs
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	mov loc1 = cr.ifs
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	movl loc2 = PFM_MASK ;;
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	movl loc2 = PFM_MASK ;;
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	and loc1 = loc2, loc1 ;;
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	and loc1 = loc2, loc1 ;;
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	mov cr.ifs = loc1 ;;			/* prevent decrementing BSP by rfi */
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	mov cr.ifs = loc1 ;;			/* prevent decrementing BSP by rfi */
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	invala
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	invala
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172
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	mov loc1 = ar.rsc ;;
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	mov loc1 = ar.rsc ;;
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	and loc1 = ~3, loc1 ;;
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	and loc1 = ~3, loc1 ;;
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	mov ar.rsc = loc1 ;;			/* put RSE into enforced lazy mode */
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	mov ar.rsc = loc1 ;;			/* put RSE into enforced lazy mode */
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	flushrs ;;
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	flushrs ;;
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	mov ar.bspstore = in2 ;;
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	mov ar.bspstore = in2 ;;
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	mov ar.rsc = in5 ;;
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	mov ar.rsc = in5 ;;
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	mov r8 = in3
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	mov r8 = in3
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	rfi ;;
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	rfi ;;
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