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| Rev 870 | Rev 879 | ||
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| Line 43... | Line 43... | ||
| 43 | 43 | ||
| 44 | #endif |
44 | #endif |
| 45 | 45 | ||
| 46 | #define PAGE_SIZE FRAME_SIZE |
46 | #define PAGE_SIZE FRAME_SIZE |
| 47 | #define PAGE_WIDTH FRAME_WIDTH |
47 | #define PAGE_WIDTH FRAME_WIDTH |
| 48 | #define KERNEL_PAGE_WIDTH 26 |
48 | #define KERNEL_PAGE_WIDTH 28 |
| 49 | 49 | ||
| 50 | 50 | ||
| 51 | 51 | ||
| 52 | #define SET_PTL0_ADDRESS_ARCH(x) /**< To be removed as situation permits. */ |
52 | #define SET_PTL0_ADDRESS_ARCH(x) /**< To be removed as situation permits. */ |
| 53 | 53 | ||
| Line 227... | Line 227... | ||
| 227 | * @return Current contents of rr[i]. |
227 | * @return Current contents of rr[i]. |
| 228 | */ |
228 | */ |
| 229 | static inline __u64 rr_read(index_t i) |
229 | static inline __u64 rr_read(index_t i) |
| 230 | { |
230 | { |
| 231 | __u64 ret; |
231 | __u64 ret; |
| 232 | - | ||
| 233 | ASSERT(i < REGION_REGISTERS); |
232 | ASSERT(i < REGION_REGISTERS); |
| - | 233 | i=i<<VRN_SHIFT; |
|
| 234 | __asm__ volatile ("mov %0 = rr[%1]\n" : "=r" (ret) : "r" (i)); |
234 | __asm__ volatile ("mov %0 = rr[%1]\n" : "=r" (ret) : "r" (i)); |
| 235 | 235 | ||
| 236 | return ret; |
236 | return ret; |
| 237 | } |
237 | } |
| 238 | 238 | ||
| Line 243... | Line 243... | ||
| 243 | * @param v Value to be written to rr[i]. |
243 | * @param v Value to be written to rr[i]. |
| 244 | */ |
244 | */ |
| 245 | static inline void rr_write(index_t i, __u64 v) |
245 | static inline void rr_write(index_t i, __u64 v) |
| 246 | { |
246 | { |
| 247 | ASSERT(i < REGION_REGISTERS); |
247 | ASSERT(i < REGION_REGISTERS); |
| - | 248 | i=i<<VRN_SHIFT; |
|
| 248 | __asm__ volatile ( |
249 | __asm__ volatile ( |
| 249 | "mov rr[%0] = %1;;\n" |
250 | "mov rr[%0] = %1;;\n" |
| 250 | : |
251 | : |
| 251 | : "r" (i), "r" (v)); |
252 | : "r" (i), "r" (v)); |
| 252 | } |
253 | } |