Rev 747 | Rev 749 | Go to most recent revision | Show entire file | Ignore whitespace | Details | Blame | Last modification | View Log | RSS feed
| Rev 747 | Rev 748 | ||
|---|---|---|---|
| Line 44... | Line 44... | ||
| 44 | 44 | ||
| 45 | #define GET_PTL0_ADDRESS_ARCH() ((pte_t *) 0) |
45 | #define GET_PTL0_ADDRESS_ARCH() ((pte_t *) 0) |
| 46 | #define SET_PTL0_ADDRESS_ARCH(ptl0) |
46 | #define SET_PTL0_ADDRESS_ARCH(ptl0) |
| 47 | 47 | ||
| 48 | /** Implementation of page hash table interface. */ |
48 | /** Implementation of page hash table interface. */ |
| 49 | #define HT_ENTRIES_ARCH 0 |
49 | #define HT_ENTRIES_ARCH (VHPT_SIZE/sizeof(pte_t)) |
| 50 | #define HT_HASH_ARCH(page, asid) 0 |
50 | #define HT_HASH_ARCH(page, asid) vhpt_hash((page), (asid)) |
| 51 | #define HT_COMPARE_ARCH(page, asid, t) 0 |
51 | #define HT_COMPARE_ARCH(page, asid, t) 0 |
| 52 | #define HT_SLOT_EMPTY_ARCH(t) 1 |
52 | #define HT_SLOT_EMPTY_ARCH(t) 1 |
| 53 | #define HT_INVALIDATE_SLOT_ARCH(t) |
53 | #define HT_INVALIDATE_SLOT_ARCH(t) |
| 54 | #define HT_GET_NEXT_ARCH(t) 0 |
54 | #define HT_GET_NEXT_ARCH(t) 0 |
| 55 | #define HT_SET_NEXT_ARCH(t, s) |
55 | #define HT_SET_NEXT_ARCH(t, s) |
| 56 | #define HT_SET_RECORD_ARCH(t, page, asid, frame, flags) |
56 | #define HT_SET_RECORD_ARCH(t, page, asid, frame, flags) |
| 57 | 57 | ||
| - | 58 | #define VRN_SHIFT 61 |
|
| - | 59 | #define VRN_MASK (7LL << VRN_SHIFT) |
|
| - | 60 | ||
| 58 | #define VRN_KERNEL 0 |
61 | #define VRN_KERNEL 0 |
| - | 62 | #define VRN_WORK 1LL |
|
| 59 | #define REGION_REGISTERS 8 |
63 | #define REGION_REGISTERS 8 |
| 60 | 64 | ||
| 61 | #define VHPT_WIDTH 20 /* 1M */ |
65 | #define VHPT_WIDTH 20 /* 1M */ |
| 62 | #define VHPT_SIZE (1<<VHPT_WIDTH) |
66 | #define VHPT_SIZE (1<<VHPT_WIDTH) |
| 63 | 67 | ||
| Line 195... | Line 199... | ||
| 195 | */ |
199 | */ |
| 196 | static inline __u64 rr_read(index_t i) |
200 | static inline __u64 rr_read(index_t i) |
| 197 | { |
201 | { |
| 198 | __u64 ret; |
202 | __u64 ret; |
| 199 | 203 | ||
| 200 | // ASSERT(i < REGION_REGISTERS); |
204 | ASSERT(i < REGION_REGISTERS); |
| 201 | __asm__ volatile ("mov %0 = rr[%1]\n" : "=r" (ret) : "r" (i)); |
205 | __asm__ volatile ("mov %0 = rr[%1]\n" : "=r" (ret) : "r" (i)); |
| 202 | 206 | ||
| 203 | return ret; |
207 | return ret; |
| 204 | } |
208 | } |
| 205 | 209 | ||
| Line 209... | Line 213... | ||
| 209 | * @param i Region register index. |
213 | * @param i Region register index. |
| 210 | * @param v Value to be written to rr[i]. |
214 | * @param v Value to be written to rr[i]. |
| 211 | */ |
215 | */ |
| 212 | static inline void rr_write(index_t i, __u64 v) |
216 | static inline void rr_write(index_t i, __u64 v) |
| 213 | { |
217 | { |
| 214 | // ASSERT(i < REGION_REGISTERS); |
218 | ASSERT(i < REGION_REGISTERS); |
| 215 | __asm__ volatile ("mov rr[%0] = %1\n" : : "r" (i), "r" (v)); |
219 | __asm__ volatile ("mov rr[%0] = %1\n" : : "r" (i), "r" (v)); |
| 216 | } |
220 | } |
| 217 | 221 | ||
| 218 | /** Read Page Table Register. |
222 | /** Read Page Table Register. |
| 219 | * |
223 | * |
| Line 236... | Line 240... | ||
| 236 | { |
240 | { |
| 237 | __asm__ volatile ("mov cr.pta = %0\n" : : "r" (v)); |
241 | __asm__ volatile ("mov cr.pta = %0\n" : : "r" (v)); |
| 238 | } |
242 | } |
| 239 | 243 | ||
| 240 | extern void page_arch_init(void); |
244 | extern void page_arch_init(void); |
| - | 245 | extern pte_t *vhpt_hash(__address page, asid_t asid); |
|
| 241 | 246 | ||
| 242 | #endif |
247 | #endif |