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/*
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/*
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 * Copyright (C) 2005 Jakub Jermar
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 * Copyright (C) 2005 Jakub Jermar
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 * All rights reserved.
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 * All rights reserved.
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 *
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 *
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 * Redistribution and use in source and binary forms, with or without
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 * Redistribution and use in source and binary forms, with or without
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 * modification, are permitted provided that the following conditions
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 * modification, are permitted provided that the following conditions
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 * are met:
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 * are met:
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 *
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 *
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 * - Redistributions of source code must retain the above copyright
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 * - Redistributions of source code must retain the above copyright
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 *   notice, this list of conditions and the following disclaimer.
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 *   notice, this list of conditions and the following disclaimer.
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 * - Redistributions in binary form must reproduce the above copyright
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 * - Redistributions in binary form must reproduce the above copyright
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 *   notice, this list of conditions and the following disclaimer in the
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 *   notice, this list of conditions and the following disclaimer in the
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 *   documentation and/or other materials provided with the distribution.
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 *   documentation and/or other materials provided with the distribution.
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 * - The name of the author may not be used to endorse or promote products
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 * - The name of the author may not be used to endorse or promote products
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 *   derived from this software without specific prior written permission.
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 *   derived from this software without specific prior written permission.
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 *
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 *
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 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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 */
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 */
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 /** @addtogroup ia64interrupt
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 /** @addtogroup ia64interrupt
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 * @{
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 * @{
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 */
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 */
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/** @file
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/** @file
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 */
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 */
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#ifndef __ia64_INTERRUPT_H__
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#ifndef __ia64_INTERRUPT_H__
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#define __ia64_INTERRUPT_H__
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#define __ia64_INTERRUPT_H__
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#include <typedefs.h>
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#include <typedefs.h>
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#include <arch/types.h>
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#include <arch/types.h>
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#include <arch/register.h>
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#include <arch/register.h>
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#define IRQ_COUNT               257 /* 256 NOT suppotred IRQS*//* TODO */
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#define IRQ_COUNT               257 /* 256 NOT suppotred IRQS*//* TODO */
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#define IRQ_KBD                 256 /* One simulated interrupt for ski simulator keyboard*/
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#define IRQ_KBD                 256 /* One simulated interrupt for ski simulator keyboard*/
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/** External Interrupt vectors. */
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/** External Interrupt vectors. */
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#define INTERRUPT_TIMER     0
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#define INTERRUPT_TIMER     0
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#define INTERRUPT_SPURIOUS  15
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#define INTERRUPT_SPURIOUS  15
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/** General Exception codes. */
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/** General Exception codes. */
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#define GE_ILLEGALOP        0
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#define GE_ILLEGALOP        0
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#define GE_PRIVOP       1
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#define GE_PRIVOP       1
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#define GE_PRIVREG      2
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#define GE_PRIVREG      2
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#define GE_RESREGFLD        3
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#define GE_RESREGFLD        3
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#define GE_DISBLDISTRAN     4
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#define GE_DISBLDISTRAN     4
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#define GE_ILLEGALDEP       8
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#define GE_ILLEGALDEP       8
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#define EOI 0       /**< The actual value doesn't matter. */
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#define EOI 0       /**< The actual value doesn't matter. */
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struct istate {
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struct istate {
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    __r128 f2;
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    __r128 f2;
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    __r128 f3;
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    __r128 f3;
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    __r128 f4;
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    __r128 f4;
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    __r128 f5;
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    __r128 f5;
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    __r128 f6;
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    __r128 f6;
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    __r128 f7;
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    __r128 f7;
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    __r128 f8;
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    __r128 f8;
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    __r128 f9;
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    __r128 f9;
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    __r128 f10;
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    __r128 f10;
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    __r128 f11;
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    __r128 f11;
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    __r128 f12;
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    __r128 f12;
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    __r128 f13;
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    __r128 f13;
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    __r128 f14;
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    __r128 f14;
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    __r128 f15;
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    __r128 f15;
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    __r128 f16;
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    __r128 f16;
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    __r128 f17;
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    __r128 f17;
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    __r128 f18;
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    __r128 f18;
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    __r128 f19;
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    __r128 f19;
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    __r128 f20;
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    __r128 f20;
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    __r128 f21;
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    __r128 f21;
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    __r128 f22;
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    __r128 f22;
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    __r128 f23;
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    __r128 f23;
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    __r128 f24;
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    __r128 f24;
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    __r128 f25;
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    __r128 f25;
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    __r128 f26;
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    __r128 f26;
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    __r128 f27;
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    __r128 f27;
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    __r128 f28;
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    __r128 f28;
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    __r128 f29;
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    __r128 f29;
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    __r128 f30;
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    __r128 f30;
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    __r128 f31;
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    __r128 f31;
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    __address ar_bsp;
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    uintptr_t ar_bsp;
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    __address ar_bspstore;
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    uintptr_t ar_bspstore;
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    __address ar_bspstore_new;
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    uintptr_t ar_bspstore_new;
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    __u64 ar_rnat;
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    uint64_t ar_rnat;
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    __u64 ar_ifs;
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    uint64_t ar_ifs;
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    __u64 ar_pfs;
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    uint64_t ar_pfs;
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    __u64 ar_rsc;
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    uint64_t ar_rsc;
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    __address cr_ifa;
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    uintptr_t cr_ifa;
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    cr_isr_t cr_isr;
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    cr_isr_t cr_isr;
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    __address cr_iipa;
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    uintptr_t cr_iipa;
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    psr_t cr_ipsr;
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    psr_t cr_ipsr;
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    __address cr_iip;
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    uintptr_t cr_iip;
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    __u64 pr;
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    uint64_t pr;
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    __address sp;
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    uintptr_t sp;
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    /*
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    /*
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     * The following variables are defined only for break_instruction handler.
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     * The following variables are defined only for break_instruction handler.
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     */
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     */
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    __u64 in0;
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    uint64_t in0;
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    __u64 in1;
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    uint64_t in1;
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    __u64 in2;
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    uint64_t in2;
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    __u64 in3;
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    uint64_t in3;
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    __u64 in4;
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    uint64_t in4;
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};
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};
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static inline void istate_set_retaddr(istate_t *istate, __address retaddr)
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static inline void istate_set_retaddr(istate_t *istate, uintptr_t retaddr)
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{
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{
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    istate->cr_iip = retaddr;
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    istate->cr_iip = retaddr;
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    istate->cr_ipsr.ri = 0;     /* return to instruction slot #0 */
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    istate->cr_ipsr.ri = 0;     /* return to instruction slot #0 */
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}
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}
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static inline __native istate_get_pc(istate_t *istate)
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static inline unative_t istate_get_pc(istate_t *istate)
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{
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{
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    return istate->cr_iip;
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    return istate->cr_iip;
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}
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}
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#include <panic.h>
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#include <panic.h>
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static inline int istate_from_uspace(istate_t *istate)
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static inline int istate_from_uspace(istate_t *istate)
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{
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{
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    return (istate->cr_iip)<0xe000000000000000ULL;
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    return (istate->cr_iip)<0xe000000000000000ULL;
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}
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}
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extern void *ivt;
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extern void *ivt;
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extern void general_exception(__u64 vector, istate_t *istate);
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extern void general_exception(uint64_t vector, istate_t *istate);
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extern int break_instruction(__u64 vector, istate_t *istate);
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extern int break_instruction(uint64_t vector, istate_t *istate);
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extern void universal_handler(__u64 vector, istate_t *istate);
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extern void universal_handler(uint64_t vector, istate_t *istate);
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extern void nop_handler(__u64 vector, istate_t *istate);
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extern void nop_handler(uint64_t vector, istate_t *istate);
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extern void external_interrupt(__u64 vector, istate_t *istate);
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extern void external_interrupt(uint64_t vector, istate_t *istate);
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extern void virtual_interrupt(__u64 irq, void *param);
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extern void virtual_interrupt(uint64_t irq, void *param);
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extern void disabled_fp_register(__u64 vector, istate_t *istate);
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extern void disabled_fp_register(uint64_t vector, istate_t *istate);
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#endif
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#endif
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 /** @}
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 /** @}
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 */
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 */
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