WebSVN – HelenOS-historic – Diff – /kernel/trunk/arch/ia32/src/smp/apic.c


/*
 * Copyright (C) 2001-2004 Jakub Jermar
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * - Redistributions of source code must retain the above copyright
 *   notice, this list of conditions and the following disclaimer.
 * - Redistributions in binary form must reproduce the above copyright
 *   notice, this list of conditions and the following disclaimer in the
 *   documentation and/or other materials provided with the distribution.
 * - The name of the author may not be used to endorse or promote products
 *   derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
 /** @addtogroup ia32  
 * @{
 */
/** @file
 */
 
#include <arch/types.h>
#include <arch/smp/apic.h>
#include <arch/smp/ap.h>
#include <arch/smp/mps.h>
#include <arch/boot/boot.h>
#include <mm/page.h>
#include <time/delay.h>
#include <interrupt.h>
#include <arch/interrupt.h>
#include <print.h>
#include <arch/asm.h>
#include <arch.h>
 
#ifdef CONFIG_SMP
 
/*
 * Advanced Programmable Interrupt Controller for SMP systems.
 * Tested on:
 *  Bochs 2.0.2 - Bochs 2.2.6 with 2-8 CPUs
 *  Simics 2.0.28 - Simics 2.2.19 2-15 CPUs
 *  VMware Workstation 5.5 with 2 CPUs
 *  QEMU 0.8.0 with 2-15 CPUs
 *  ASUS P/I-P65UP5 + ASUS C-P55T2D REV. 1.41 with 2x 200Mhz Pentium CPUs
 *  ASUS PCH-DL with 2x 3000Mhz Pentium 4 Xeon (HT) CPUs
 *  MSI K7D Master-L with 2x 2100MHz Athlon MP CPUs
 */
 
/*
 * These variables either stay configured as initilalized, or are changed by
 * the MP configuration code.
 *
 * Pay special attention to the volatile keyword. Without it, gcc -O2 would
 * optimize the code too much and accesses to l_apic and io_apic, that must
 * always be 32-bit, would use byte oriented instructions.
 */
volatile __u32 *l_apic = (__u32 *) 0xfee00000;
volatile __u32 *io_apic = (__u32 *) 0xfec00000;
 
__u32 apic_id_mask = 0;
 
static int apic_poll_errors(void);
 
#ifdef LAPIC_VERBOSE
static char *delmod_str[] = {
    "Fixed",
    "Lowest Priority",
    "SMI",
    "Reserved",
    "NMI",
    "INIT",
    "STARTUP",
    "ExtInt"
};
 
static char *destmod_str[] = {
    "Physical",
    "Logical"
};
 
static char *trigmod_str[] = {
    "Edge",
    "Level"
};
 
static char *mask_str[] = {
    "Unmasked",
    "Masked"
};
 
static char *delivs_str[] = {
    "Idle",
    "Send Pending"
};
 
static char *tm_mode_str[] = {
    "One-shot",
    "Periodic"
};
 
static char *intpol_str[] = {
    "Polarity High",
    "Polarity Low"
};
#endif /* LAPIC_VERBOSE */
 
 
static void apic_spurious(int n, istate_t *istate);
static void l_apic_timer_interrupt(int n, istate_t *istate);
 
/** Initialize APIC on BSP. */
void apic_init(void)
{
    io_apic_id_t idreg;
    int i;
 
    exc_register(VECTOR_APIC_SPUR, "apic_spurious", (iroutine) apic_spurious);
 
    enable_irqs_function = io_apic_enable_irqs;
    disable_irqs_function = io_apic_disable_irqs;
    eoi_function = l_apic_eoi;
   
    /*
     * Configure interrupt routing.
     * IRQ 0 remains masked as the time signal is generated by l_apic's themselves.
     * Other interrupts will be forwarded to the lowest priority CPU.
     */
    io_apic_disable_irqs(0xffff);
    exc_register(VECTOR_CLK, "l_apic_timer", (iroutine) l_apic_timer_interrupt);
    for (i = 0; i < IRQ_COUNT; i++) {
        int pin;
   
        if ((pin = smp_irq_to_pin(i)) != -1) {
            io_apic_change_ioredtbl(pin, DEST_ALL, IVT_IRQBASE+i, LOPRI);
        }
    }
   
    /*
     * Ensure that io_apic has unique ID.
     */
    idreg.value = io_apic_read(IOAPICID);
    if ((1<<idreg.apic_id) & apic_id_mask) {    /* see if IO APIC ID is used already */
        for (i = 0; i < APIC_ID_COUNT; i++) {
            if (!((1<<i) & apic_id_mask)) {
                idreg.apic_id = i;
                io_apic_write(IOAPICID, idreg.value);
                break;
            }
        }
    }
 
    /*
     * Configure the BSP's lapic.
     */
    l_apic_init();
 
    l_apic_debug();
}
 
/** APIC spurious interrupt handler.
 *
 * @param n Interrupt vector.
 * @param stack Interrupted stack.
 */
void apic_spurious(int n, istate_t *istate)
{
#ifdef CONFIG_DEBUG
    printf("cpu%d: APIC spurious interrupt\n", CPU->id);
#endif
}
 
/** Poll for APIC errors.
 *
 * Examine Error Status Register and report all errors found.
 *
 * @return 0 on error, 1 on success.
 */
int apic_poll_errors(void)
{
    esr_t esr;
   
    esr.value = l_apic[ESR];
   
    if (esr.send_checksum_error)
        printf("Send Checksum Error\n");
    if (esr.receive_checksum_error)
        printf("Receive Checksum Error\n");
    if (esr.send_accept_error)
        printf("Send Accept Error\n");
    if (esr.receive_accept_error)
        printf("Receive Accept Error\n");
    if (esr.send_illegal_vector)
        printf("Send Illegal Vector\n");
    if (esr.received_illegal_vector)
        printf("Received Illegal Vector\n");
    if (esr.illegal_register_address)
        printf("Illegal Register Address\n");
 
    return !esr.err_bitmap;
}
 
/** Send all CPUs excluding CPU IPI vector.
 *
 * @param vector Interrupt vector to be sent.
 *
 * @return 0 on failure, 1 on success.
 */
int l_apic_broadcast_custom_ipi(__u8 vector)
{
    icr_t icr;
 
    icr.lo = l_apic[ICRlo];
    icr.delmod = DELMOD_FIXED;
    icr.destmod = DESTMOD_LOGIC;
    icr.level = LEVEL_ASSERT;
    icr.shorthand = SHORTHAND_ALL_EXCL;
    icr.trigger_mode = TRIGMOD_LEVEL;
    icr.vector = vector;
 
    l_apic[ICRlo] = icr.lo;
 
    icr.lo = l_apic[ICRlo];
    if (icr.delivs == DELIVS_PENDING) {
#ifdef CONFIG_DEBUG
        printf("IPI is pending.\n");
#endif
    }
 
    return apic_poll_errors();
}
 
/** Universal Start-up Algorithm for bringing up the AP processors.
 *
 * @param apicid APIC ID of the processor to be brought up.
 *
 * @return 0 on failure, 1 on success.
 */
int l_apic_send_init_ipi(__u8 apicid)
{
    icr_t icr;
    int i;
 
    /*
     * Read the ICR register in and zero all non-reserved fields.
     */
    icr.lo = l_apic[ICRlo];
    icr.hi = l_apic[ICRhi];
   
    icr.delmod = DELMOD_INIT;
    icr.destmod = DESTMOD_PHYS;
    icr.level = LEVEL_ASSERT;
    icr.trigger_mode = TRIGMOD_LEVEL;
    icr.shorthand = SHORTHAND_NONE;
    icr.vector = 0;
    icr.dest = apicid;
   
    l_apic[ICRhi] = icr.hi;
    l_apic[ICRlo] = icr.lo;
 
    /*
     * According to MP Specification, 20us should be enough to
     * deliver the IPI.
     */
    delay(20);
 
    if (!apic_poll_errors())
        return 0;
 
    icr.lo = l_apic[ICRlo];
    if (icr.delivs == DELIVS_PENDING) {
#ifdef CONFIG_DEBUG
        printf("IPI is pending.\n");
#endif
    }
 
    icr.delmod = DELMOD_INIT;
    icr.destmod = DESTMOD_PHYS;
    icr.level = LEVEL_DEASSERT;
    icr.shorthand = SHORTHAND_NONE;
    icr.trigger_mode = TRIGMOD_LEVEL;
    icr.vector = 0;
    l_apic[ICRlo] = icr.lo;
 
    /*
     * Wait 10ms as MP Specification specifies.
     */
    delay(10000);
 
    if (!is_82489DX_apic(l_apic[LAVR])) {
        /*
         * If this is not 82489DX-based l_apic we must send two STARTUP IPI's.
         */
        for (i = 0; i<2; i++) {
            icr.lo = l_apic[ICRlo];
            icr.vector = ((__address) ap_boot) / 4096; /* calculate the reset vector */
            icr.delmod = DELMOD_STARTUP;
            icr.destmod = DESTMOD_PHYS;
            icr.level = LEVEL_ASSERT;
            icr.shorthand = SHORTHAND_NONE;
            icr.trigger_mode = TRIGMOD_LEVEL;
            l_apic[ICRlo] = icr.lo;
            delay(200);
        }
    }
   
    return apic_poll_errors();
}
 
/** Initialize Local APIC. */
void l_apic_init(void)
{
    lvt_error_t error;
    lvt_lint_t lint;
    tpr_t tpr;
    svr_t svr;
    icr_t icr;
    tdcr_t tdcr;
    lvt_tm_t tm;
    ldr_t ldr;
    dfr_t dfr;
    __u32 t1, t2;
 
    /* Initialize LVT Error register. */
    error.value = l_apic[LVT_Err];
    error.masked = true;
    l_apic[LVT_Err] = error.value;
 
    /* Initialize LVT LINT0 register. */
    lint.value = l_apic[LVT_LINT0];
    lint.masked = true;
    l_apic[LVT_LINT0] = lint.value;
 
    /* Initialize LVT LINT1 register. */
    lint.value = l_apic[LVT_LINT1];
    lint.masked = true;
    l_apic[LVT_LINT1] = lint.value;
 
    /* Task Priority Register initialization. */
    tpr.value = l_apic[TPR];
    tpr.pri_sc = 0;
    tpr.pri = 0;
    l_apic[TPR] = tpr.value;
   
    /* Spurious-Interrupt Vector Register initialization. */
    svr.value = l_apic[SVR];
    svr.vector = VECTOR_APIC_SPUR;
    svr.lapic_enabled = true;
    svr.focus_checking = true;
    l_apic[SVR] = svr.value;
 
    if (CPU->arch.family >= 6)
        enable_l_apic_in_msr();
   
    /* Interrupt Command Register initialization. */
    icr.lo = l_apic[ICRlo];
    icr.delmod = DELMOD_INIT;
    icr.destmod = DESTMOD_PHYS;
    icr.level = LEVEL_DEASSERT;
    icr.shorthand = SHORTHAND_ALL_INCL;
    icr.trigger_mode = TRIGMOD_LEVEL;
    l_apic[ICRlo] = icr.lo;
   
    /* Timer Divide Configuration Register initialization. */
    tdcr.value = l_apic[TDCR];
    tdcr.div_value = DIVIDE_1;
    l_apic[TDCR] = tdcr.value;
 
    /* Program local timer. */
    tm.value = l_apic[LVT_Tm];
    tm.vector = VECTOR_CLK;
    tm.mode = TIMER_PERIODIC;
    tm.masked = false;
    l_apic[LVT_Tm] = tm.value;
 
    /*
     * Measure and configure the timer to generate timer
     * interrupt with period 1s/HZ seconds.
     */
    t1 = l_apic[CCRT];
    l_apic[ICRT] = 0xffffffff;
 
    while (l_apic[CCRT] == t1)
        ;
       
    t1 = l_apic[CCRT];
    delay(1000000/HZ);
    t2 = l_apic[CCRT];
   
    l_apic[ICRT] = t1-t2;
   
    /* Program Logical Destination Register. */
    ldr.value = l_apic[LDR];
    if (CPU->id < sizeof(CPU->id)*8)    /* size in bits */
        ldr.id = (1<<CPU->id);
    l_apic[LDR] = ldr.value;
   
    /* Program Destination Format Register for Flat mode. */
    dfr.value = l_apic[DFR];
    dfr.model = MODEL_FLAT;
    l_apic[DFR] = dfr.value;
}
 
/** Local APIC End of Interrupt. */
void l_apic_eoi(void)
{
    l_apic[EOI] = 0;
}
 
/** Dump content of Local APIC registers. */
void l_apic_debug(void)
{
#ifdef LAPIC_VERBOSE
    lvt_tm_t tm;
    lvt_lint_t lint;
    lvt_error_t error; 
   
    printf("LVT on cpu%d, LAPIC ID: %d\n", CPU->id, l_apic_id());
 
    tm.value = l_apic[LVT_Tm];
    printf("LVT Tm: vector=%hhd, %s, %s, %s\n", tm.vector, delivs_str[tm.delivs], mask_str[tm.masked], tm_mode_str[tm.mode]);
    lint.value = l_apic[LVT_LINT0];
    printf("LVT LINT0: vector=%hhd, %s, %s, %s, irr=%d, %s, %s\n", tm.vector, delmod_str[lint.delmod], delivs_str[lint.delivs], intpol_str[lint.intpol], lint.irr, trigmod_str[lint.trigger_mode], mask_str[lint.masked]);
    lint.value = l_apic[LVT_LINT1];
    printf("LVT LINT1: vector=%hhd, %s, %s, %s, irr=%d, %s, %s\n", tm.vector, delmod_str[lint.delmod], delivs_str[lint.delivs], intpol_str[lint.intpol], lint.irr, trigmod_str[lint.trigger_mode], mask_str[lint.masked]); 
    error.value = l_apic[LVT_Err];
    printf("LVT Err: vector=%hhd, %s, %s\n", error.vector, delivs_str[error.delivs], mask_str[error.masked]);
#endif
}
 
/** Local APIC Timer Interrupt.
 *
 * @param n Interrupt vector number.
 * @param stack Interrupted stack.
 */
void l_apic_timer_interrupt(int n, istate_t *istate)
{
    l_apic_eoi();
    clock();
}
 
/** Get Local APIC ID.
 *
 * @return Local APIC ID.
 */
__u8 l_apic_id(void)
{
    l_apic_id_t idreg;
   
    idreg.value = l_apic[L_APIC_ID];
    return idreg.apic_id;
}
 
/** Read from IO APIC register.
 *
 * @param address IO APIC register address.
 *
 * @return Content of the addressed IO APIC register.
 */
__u32 io_apic_read(__u8 address)
{
    io_regsel_t regsel;
   
    regsel.value = io_apic[IOREGSEL];
    regsel.reg_addr = address;
    io_apic[IOREGSEL] = regsel.value;
    return io_apic[IOWIN];
}
 
/** Write to IO APIC register.
 *
 * @param address IO APIC register address.
 * @param Content to be written to the addressed IO APIC register.
 */
void io_apic_write(__u8 address, __u32 x)
{
    io_regsel_t regsel;
   
    regsel.value = io_apic[IOREGSEL];
    regsel.reg_addr = address;
    io_apic[IOREGSEL] = regsel.value;
    io_apic[IOWIN] = x;
}
 
/** Change some attributes of one item in I/O Redirection Table.
 *
 * @param pin IO APIC pin number.
 * @param dest Interrupt destination address.
 * @param v Interrupt vector to trigger.
 * @param flags Flags.
 */
void io_apic_change_ioredtbl(int pin, int dest, __u8 v, int flags)
{
    io_redirection_reg_t reg;
    int dlvr = DELMOD_FIXED;
   
    if (flags & LOPRI)
        dlvr = DELMOD_LOWPRI;
 
    reg.lo = io_apic_read(IOREDTBL + pin*2);
    reg.hi = io_apic_read(IOREDTBL + pin*2 + 1);
   
    reg.dest = dest;
    reg.destmod = DESTMOD_LOGIC;
    reg.trigger_mode = TRIGMOD_EDGE;
    reg.intpol = POLARITY_HIGH;
    reg.delmod = dlvr;
    reg.intvec = v;
 
    io_apic_write(IOREDTBL + pin*2, reg.lo);
    io_apic_write(IOREDTBL + pin*2 + 1, reg.hi);
}
 
/** Mask IRQs in IO APIC.
 *
 * @param irqmask Bitmask of IRQs to be masked (0 = do not mask, 1 = mask).
 */
void io_apic_disable_irqs(__u16 irqmask)
{
    io_redirection_reg_t reg;
    int i, pin;
   
    for (i=0;i<16;i++) {
        if (irqmask & (1<<i)) {
            /*
             * Mask the signal input in IO APIC if there is a
             * mapping for the respective IRQ number.
             */
            pin = smp_irq_to_pin(i);
            if (pin != -1) {
                reg.lo = io_apic_read(IOREDTBL + pin*2);
                reg.masked = true;
                io_apic_write(IOREDTBL + pin*2, reg.lo);
            }
           
        }
    }
}
 
/** Unmask IRQs in IO APIC.
 *
 * @param irqmask Bitmask of IRQs to be unmasked (0 = do not unmask, 1 = unmask).
 */
void io_apic_enable_irqs(__u16 irqmask)
{
    int i, pin;
    io_redirection_reg_t reg;  
   
    for (i=0;i<16;i++) {
        if (irqmask & (1<<i)) {
            /*
             * Unmask the signal input in IO APIC if there is a
             * mapping for the respective IRQ number.
             */
            pin = smp_irq_to_pin(i);
            if (pin != -1) {
                reg.lo = io_apic_read(IOREDTBL + pin*2);
                reg.masked = false;
                io_apic_write(IOREDTBL + pin*2, reg.lo);
            }
           
        }
    }
}
 
#endif /* CONFIG_SMP */
 
 /** @}
 */
 
 

Rev 1684	Rev 1702
1	/*	1	/*
2	* Copyright (C) 2001-2004 Jakub Jermar	2	* Copyright (C) 2001-2004 Jakub Jermar
3	* All rights reserved.	3	* All rights reserved.
4	*	4	*
5	* Redistribution and use in source and binary forms, with or without	5	* Redistribution and use in source and binary forms, with or without
6	* modification, are permitted provided that the following conditions	6	* modification, are permitted provided that the following conditions
7	* are met:	7	* are met:
8	*	8	*
9	* - Redistributions of source code must retain the above copyright	9	* - Redistributions of source code must retain the above copyright
10	* notice, this list of conditions and the following disclaimer.	10	* notice, this list of conditions and the following disclaimer.
11	* - Redistributions in binary form must reproduce the above copyright	11	* - Redistributions in binary form must reproduce the above copyright
12	* notice, this list of conditions and the following disclaimer in the	12	* notice, this list of conditions and the following disclaimer in the
13	* documentation and/or other materials provided with the distribution.	13	* documentation and/or other materials provided with the distribution.
14	* - The name of the author may not be used to endorse or promote products	14	* - The name of the author may not be used to endorse or promote products
15	* derived from this software without specific prior written permission.	15	* derived from this software without specific prior written permission.
16	*	16	*
17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27	*/	27	*/
28		28
-		29	/** @addtogroup ia32
-		30	* @{
-		31	*/
-		32	/** @file
-		33	*/
-		34
29	#include <arch/types.h>	35	#include <arch/types.h>
30	#include <arch/smp/apic.h>	36	#include <arch/smp/apic.h>
31	#include <arch/smp/ap.h>	37	#include <arch/smp/ap.h>
32	#include <arch/smp/mps.h>	38	#include <arch/smp/mps.h>
33	#include <arch/boot/boot.h>	39	#include <arch/boot/boot.h>
34	#include <mm/page.h>	40	#include <mm/page.h>
35	#include <time/delay.h>	41	#include <time/delay.h>
36	#include <interrupt.h>	42	#include <interrupt.h>
37	#include <arch/interrupt.h>	43	#include <arch/interrupt.h>
38	#include <print.h>	44	#include <print.h>
39	#include <arch/asm.h>	45	#include <arch/asm.h>
40	#include <arch.h>	46	#include <arch.h>
41		47
42	#ifdef CONFIG_SMP	48	#ifdef CONFIG_SMP
43		49
44	/*	50	/*
45	* Advanced Programmable Interrupt Controller for SMP systems.	51	* Advanced Programmable Interrupt Controller for SMP systems.
46	* Tested on:	52	* Tested on:
47	* Bochs 2.0.2 - Bochs 2.2.6 with 2-8 CPUs	53	* Bochs 2.0.2 - Bochs 2.2.6 with 2-8 CPUs
48	* Simics 2.0.28 - Simics 2.2.19 2-15 CPUs	54	* Simics 2.0.28 - Simics 2.2.19 2-15 CPUs
49	* VMware Workstation 5.5 with 2 CPUs	55	* VMware Workstation 5.5 with 2 CPUs
50	* QEMU 0.8.0 with 2-15 CPUs	56	* QEMU 0.8.0 with 2-15 CPUs
51	* ASUS P/I-P65UP5 + ASUS C-P55T2D REV. 1.41 with 2x 200Mhz Pentium CPUs	57	* ASUS P/I-P65UP5 + ASUS C-P55T2D REV. 1.41 with 2x 200Mhz Pentium CPUs
52	* ASUS PCH-DL with 2x 3000Mhz Pentium 4 Xeon (HT) CPUs	58	* ASUS PCH-DL with 2x 3000Mhz Pentium 4 Xeon (HT) CPUs
53	* MSI K7D Master-L with 2x 2100MHz Athlon MP CPUs	59	* MSI K7D Master-L with 2x 2100MHz Athlon MP CPUs
54	*/	60	*/
55		61
56	/*	62	/*
57	* These variables either stay configured as initilalized, or are changed by	63	* These variables either stay configured as initilalized, or are changed by
58	* the MP configuration code.	64	* the MP configuration code.
59	*	65	*
60	* Pay special attention to the volatile keyword. Without it, gcc -O2 would	66	* Pay special attention to the volatile keyword. Without it, gcc -O2 would
61	* optimize the code too much and accesses to l_apic and io_apic, that must	67	* optimize the code too much and accesses to l_apic and io_apic, that must
62	* always be 32-bit, would use byte oriented instructions.	68	* always be 32-bit, would use byte oriented instructions.
63	*/	69	*/
64	volatile __u32 l_apic = (__u32 ) 0xfee00000;	70	volatile __u32 l_apic = (__u32 ) 0xfee00000;
65	volatile __u32 io_apic = (__u32 ) 0xfec00000;	71	volatile __u32 io_apic = (__u32 ) 0xfec00000;
66		72
67	__u32 apic_id_mask = 0;	73	__u32 apic_id_mask = 0;
68		74
69	static int apic_poll_errors(void);	75	static int apic_poll_errors(void);
70		76
71	#ifdef LAPIC_VERBOSE	77	#ifdef LAPIC_VERBOSE
72	static char *delmod_str[] = {	78	static char *delmod_str[] = {
73	"Fixed",	79	"Fixed",
74	"Lowest Priority",	80	"Lowest Priority",
75	"SMI",	81	"SMI",
76	"Reserved",	82	"Reserved",
77	"NMI",	83	"NMI",
78	"INIT",	84	"INIT",
79	"STARTUP",	85	"STARTUP",
80	"ExtInt"	86	"ExtInt"
81	};	87	};
82		88
83	static char *destmod_str[] = {	89	static char *destmod_str[] = {
84	"Physical",	90	"Physical",
85	"Logical"	91	"Logical"
86	};	92	};
87		93
88	static char *trigmod_str[] = {	94	static char *trigmod_str[] = {
89	"Edge",	95	"Edge",
90	"Level"	96	"Level"
91	};	97	};
92		98
93	static char *mask_str[] = {	99	static char *mask_str[] = {
94	"Unmasked",	100	"Unmasked",
95	"Masked"	101	"Masked"
96	};	102	};
97		103
98	static char *delivs_str[] = {	104	static char *delivs_str[] = {
99	"Idle",	105	"Idle",
100	"Send Pending"	106	"Send Pending"
101	};	107	};
102		108
103	static char *tm_mode_str[] = {	109	static char *tm_mode_str[] = {
104	"One-shot",	110	"One-shot",
105	"Periodic"	111	"Periodic"
106	};	112	};
107		113
108	static char *intpol_str[] = {	114	static char *intpol_str[] = {
109	"Polarity High",	115	"Polarity High",
110	"Polarity Low"	116	"Polarity Low"
111	};	117	};
112	#endif /* LAPIC_VERBOSE */	118	#endif /* LAPIC_VERBOSE */
113		119
114		120
115	static void apic_spurious(int n, istate_t *istate);	121	static void apic_spurious(int n, istate_t *istate);
116	static void l_apic_timer_interrupt(int n, istate_t *istate);	122	static void l_apic_timer_interrupt(int n, istate_t *istate);
117		123
118	/** Initialize APIC on BSP. */	124	/** Initialize APIC on BSP. */
119	void apic_init(void)	125	void apic_init(void)
120	{	126	{
121	io_apic_id_t idreg;	127	io_apic_id_t idreg;
122	int i;	128	int i;
123		129
124	exc_register(VECTOR_APIC_SPUR, "apic_spurious", (iroutine) apic_spurious);	130	exc_register(VECTOR_APIC_SPUR, "apic_spurious", (iroutine) apic_spurious);
125		131
126	enable_irqs_function = io_apic_enable_irqs;	132	enable_irqs_function = io_apic_enable_irqs;
127	disable_irqs_function = io_apic_disable_irqs;	133	disable_irqs_function = io_apic_disable_irqs;
128	eoi_function = l_apic_eoi;	134	eoi_function = l_apic_eoi;
129		135
130	/*	136	/*
131	* Configure interrupt routing.	137	* Configure interrupt routing.
132	* IRQ 0 remains masked as the time signal is generated by l_apic's themselves.	138	* IRQ 0 remains masked as the time signal is generated by l_apic's themselves.
133	* Other interrupts will be forwarded to the lowest priority CPU.	139	* Other interrupts will be forwarded to the lowest priority CPU.
134	*/	140	*/
135	io_apic_disable_irqs(0xffff);	141	io_apic_disable_irqs(0xffff);
136	exc_register(VECTOR_CLK, "l_apic_timer", (iroutine) l_apic_timer_interrupt);	142	exc_register(VECTOR_CLK, "l_apic_timer", (iroutine) l_apic_timer_interrupt);
137	for (i = 0; i < IRQ_COUNT; i++) {	143	for (i = 0; i < IRQ_COUNT; i++) {
138	int pin;	144	int pin;
139		145
140	if ((pin = smp_irq_to_pin(i)) != -1) {	146	if ((pin = smp_irq_to_pin(i)) != -1) {
141	io_apic_change_ioredtbl(pin, DEST_ALL, IVT_IRQBASE+i, LOPRI);	147	io_apic_change_ioredtbl(pin, DEST_ALL, IVT_IRQBASE+i, LOPRI);
142	}	148	}
143	}	149	}
144		150
145	/*	151	/*
146	* Ensure that io_apic has unique ID.	152	* Ensure that io_apic has unique ID.
147	*/	153	*/
148	idreg.value = io_apic_read(IOAPICID);	154	idreg.value = io_apic_read(IOAPICID);
149	if ((1<<idreg.apic_id) & apic_id_mask) { /* see if IO APIC ID is used already */	155	if ((1<<idreg.apic_id) & apic_id_mask) { /* see if IO APIC ID is used already */
150	for (i = 0; i < APIC_ID_COUNT; i++) {	156	for (i = 0; i < APIC_ID_COUNT; i++) {
151	if (!((1<<i) & apic_id_mask)) {	157	if (!((1<<i) & apic_id_mask)) {
152	idreg.apic_id = i;	158	idreg.apic_id = i;
153	io_apic_write(IOAPICID, idreg.value);	159	io_apic_write(IOAPICID, idreg.value);
154	break;	160	break;
155	}	161	}
156	}	162	}
157	}	163	}
158		164
159	/*	165	/*
160	* Configure the BSP's lapic.	166	* Configure the BSP's lapic.
161	*/	167	*/
162	l_apic_init();	168	l_apic_init();
163		169
164	l_apic_debug();	170	l_apic_debug();
165	}	171	}
166		172
167	/** APIC spurious interrupt handler.	173	/** APIC spurious interrupt handler.
168	*	174	*
169	* @param n Interrupt vector.	175	* @param n Interrupt vector.
170	* @param stack Interrupted stack.	176	* @param stack Interrupted stack.
171	*/	177	*/
172	void apic_spurious(int n, istate_t *istate)	178	void apic_spurious(int n, istate_t *istate)
173	{	179	{
174	#ifdef CONFIG_DEBUG	180	#ifdef CONFIG_DEBUG
175	printf("cpu%d: APIC spurious interrupt\n", CPU->id);	181	printf("cpu%d: APIC spurious interrupt\n", CPU->id);
176	#endif	182	#endif
177	}	183	}
178		184
179	/** Poll for APIC errors.	185	/** Poll for APIC errors.
180	*	186	*
181	* Examine Error Status Register and report all errors found.	187	* Examine Error Status Register and report all errors found.
182	*	188	*
183	* @return 0 on error, 1 on success.	189	* @return 0 on error, 1 on success.
184	*/	190	*/
185	int apic_poll_errors(void)	191	int apic_poll_errors(void)
186	{	192	{
187	esr_t esr;	193	esr_t esr;
188		194
189	esr.value = l_apic[ESR];	195	esr.value = l_apic[ESR];
190		196
191	if (esr.send_checksum_error)	197	if (esr.send_checksum_error)
192	printf("Send Checksum Error\n");	198	printf("Send Checksum Error\n");
193	if (esr.receive_checksum_error)	199	if (esr.receive_checksum_error)
194	printf("Receive Checksum Error\n");	200	printf("Receive Checksum Error\n");
195	if (esr.send_accept_error)	201	if (esr.send_accept_error)
196	printf("Send Accept Error\n");	202	printf("Send Accept Error\n");
197	if (esr.receive_accept_error)	203	if (esr.receive_accept_error)
198	printf("Receive Accept Error\n");	204	printf("Receive Accept Error\n");
199	if (esr.send_illegal_vector)	205	if (esr.send_illegal_vector)
200	printf("Send Illegal Vector\n");	206	printf("Send Illegal Vector\n");
201	if (esr.received_illegal_vector)	207	if (esr.received_illegal_vector)
202	printf("Received Illegal Vector\n");	208	printf("Received Illegal Vector\n");
203	if (esr.illegal_register_address)	209	if (esr.illegal_register_address)
204	printf("Illegal Register Address\n");	210	printf("Illegal Register Address\n");
205		211
206	return !esr.err_bitmap;	212	return !esr.err_bitmap;
207	}	213	}
208		214
209	/** Send all CPUs excluding CPU IPI vector.	215	/** Send all CPUs excluding CPU IPI vector.
210	*	216	*
211	* @param vector Interrupt vector to be sent.	217	* @param vector Interrupt vector to be sent.
212	*	218	*
213	* @return 0 on failure, 1 on success.	219	* @return 0 on failure, 1 on success.
214	*/	220	*/
215	int l_apic_broadcast_custom_ipi(__u8 vector)	221	int l_apic_broadcast_custom_ipi(__u8 vector)
216	{	222	{
217	icr_t icr;	223	icr_t icr;
218		224
219	icr.lo = l_apic[ICRlo];	225	icr.lo = l_apic[ICRlo];
220	icr.delmod = DELMOD_FIXED;	226	icr.delmod = DELMOD_FIXED;
221	icr.destmod = DESTMOD_LOGIC;	227	icr.destmod = DESTMOD_LOGIC;
222	icr.level = LEVEL_ASSERT;	228	icr.level = LEVEL_ASSERT;
223	icr.shorthand = SHORTHAND_ALL_EXCL;	229	icr.shorthand = SHORTHAND_ALL_EXCL;
224	icr.trigger_mode = TRIGMOD_LEVEL;	230	icr.trigger_mode = TRIGMOD_LEVEL;
225	icr.vector = vector;	231	icr.vector = vector;
226		232
227	l_apic[ICRlo] = icr.lo;	233	l_apic[ICRlo] = icr.lo;
228		234
229	icr.lo = l_apic[ICRlo];	235	icr.lo = l_apic[ICRlo];
230	if (icr.delivs == DELIVS_PENDING) {	236	if (icr.delivs == DELIVS_PENDING) {
231	#ifdef CONFIG_DEBUG	237	#ifdef CONFIG_DEBUG
232	printf("IPI is pending.\n");	238	printf("IPI is pending.\n");
233	#endif	239	#endif
234	}	240	}
235		241
236	return apic_poll_errors();	242	return apic_poll_errors();
237	}	243	}
238		244
239	/** Universal Start-up Algorithm for bringing up the AP processors.	245	/** Universal Start-up Algorithm for bringing up the AP processors.
240	*	246	*
241	* @param apicid APIC ID of the processor to be brought up.	247	* @param apicid APIC ID of the processor to be brought up.
242	*	248	*
243	* @return 0 on failure, 1 on success.	249	* @return 0 on failure, 1 on success.
244	*/	250	*/
245	int l_apic_send_init_ipi(__u8 apicid)	251	int l_apic_send_init_ipi(__u8 apicid)
246	{	252	{
247	icr_t icr;	253	icr_t icr;
248	int i;	254	int i;
249		255
250	/*	256	/*
251	* Read the ICR register in and zero all non-reserved fields.	257	* Read the ICR register in and zero all non-reserved fields.
252	*/	258	*/
253	icr.lo = l_apic[ICRlo];	259	icr.lo = l_apic[ICRlo];
254	icr.hi = l_apic[ICRhi];	260	icr.hi = l_apic[ICRhi];
255		261
256	icr.delmod = DELMOD_INIT;	262	icr.delmod = DELMOD_INIT;
257	icr.destmod = DESTMOD_PHYS;	263	icr.destmod = DESTMOD_PHYS;
258	icr.level = LEVEL_ASSERT;	264	icr.level = LEVEL_ASSERT;
259	icr.trigger_mode = TRIGMOD_LEVEL;	265	icr.trigger_mode = TRIGMOD_LEVEL;
260	icr.shorthand = SHORTHAND_NONE;	266	icr.shorthand = SHORTHAND_NONE;
261	icr.vector = 0;	267	icr.vector = 0;
262	icr.dest = apicid;	268	icr.dest = apicid;
263		269
264	l_apic[ICRhi] = icr.hi;	270	l_apic[ICRhi] = icr.hi;
265	l_apic[ICRlo] = icr.lo;	271	l_apic[ICRlo] = icr.lo;
266		272
267	/*	273	/*
268	* According to MP Specification, 20us should be enough to	274	* According to MP Specification, 20us should be enough to
269	* deliver the IPI.	275	* deliver the IPI.
270	*/	276	*/
271	delay(20);	277	delay(20);
272		278
273	if (!apic_poll_errors())	279	if (!apic_poll_errors())
274	return 0;	280	return 0;
275		281
276	icr.lo = l_apic[ICRlo];	282	icr.lo = l_apic[ICRlo];
277	if (icr.delivs == DELIVS_PENDING) {	283	if (icr.delivs == DELIVS_PENDING) {
278	#ifdef CONFIG_DEBUG	284	#ifdef CONFIG_DEBUG
279	printf("IPI is pending.\n");	285	printf("IPI is pending.\n");
280	#endif	286	#endif
281	}	287	}
282		288
283	icr.delmod = DELMOD_INIT;	289	icr.delmod = DELMOD_INIT;
284	icr.destmod = DESTMOD_PHYS;	290	icr.destmod = DESTMOD_PHYS;
285	icr.level = LEVEL_DEASSERT;	291	icr.level = LEVEL_DEASSERT;
286	icr.shorthand = SHORTHAND_NONE;	292	icr.shorthand = SHORTHAND_NONE;
287	icr.trigger_mode = TRIGMOD_LEVEL;	293	icr.trigger_mode = TRIGMOD_LEVEL;
288	icr.vector = 0;	294	icr.vector = 0;
289	l_apic[ICRlo] = icr.lo;	295	l_apic[ICRlo] = icr.lo;
290		296
291	/*	297	/*
292	* Wait 10ms as MP Specification specifies.	298	* Wait 10ms as MP Specification specifies.
293	*/	299	*/
294	delay(10000);	300	delay(10000);
295		301
296	if (!is_82489DX_apic(l_apic[LAVR])) {	302	if (!is_82489DX_apic(l_apic[LAVR])) {
297	/*	303	/*
298	* If this is not 82489DX-based l_apic we must send two STARTUP IPI's.	304	* If this is not 82489DX-based l_apic we must send two STARTUP IPI's.
299	*/	305	*/
300	for (i = 0; i<2; i++) {	306	for (i = 0; i<2; i++) {
301	icr.lo = l_apic[ICRlo];	307	icr.lo = l_apic[ICRlo];
302	icr.vector = ((__address) ap_boot) / 4096; /* calculate the reset vector */	308	icr.vector = ((__address) ap_boot) / 4096; /* calculate the reset vector */
303	icr.delmod = DELMOD_STARTUP;	309	icr.delmod = DELMOD_STARTUP;
304	icr.destmod = DESTMOD_PHYS;	310	icr.destmod = DESTMOD_PHYS;
305	icr.level = LEVEL_ASSERT;	311	icr.level = LEVEL_ASSERT;
306	icr.shorthand = SHORTHAND_NONE;	312	icr.shorthand = SHORTHAND_NONE;
307	icr.trigger_mode = TRIGMOD_LEVEL;	313	icr.trigger_mode = TRIGMOD_LEVEL;
308	l_apic[ICRlo] = icr.lo;	314	l_apic[ICRlo] = icr.lo;
309	delay(200);	315	delay(200);
310	}	316	}
311	}	317	}
312		318
313	return apic_poll_errors();	319	return apic_poll_errors();
314	}	320	}
315		321
316	/** Initialize Local APIC. */	322	/** Initialize Local APIC. */
317	void l_apic_init(void)	323	void l_apic_init(void)
318	{	324	{
319	lvt_error_t error;	325	lvt_error_t error;
320	lvt_lint_t lint;	326	lvt_lint_t lint;
321	tpr_t tpr;	327	tpr_t tpr;
322	svr_t svr;	328	svr_t svr;
323	icr_t icr;	329	icr_t icr;
324	tdcr_t tdcr;	330	tdcr_t tdcr;
325	lvt_tm_t tm;	331	lvt_tm_t tm;
326	ldr_t ldr;	332	ldr_t ldr;
327	dfr_t dfr;	333	dfr_t dfr;
328	__u32 t1, t2;	334	__u32 t1, t2;
329		335
330	/* Initialize LVT Error register. */	336	/* Initialize LVT Error register. */
331	error.value = l_apic[LVT_Err];	337	error.value = l_apic[LVT_Err];
332	error.masked = true;	338	error.masked = true;
333	l_apic[LVT_Err] = error.value;	339	l_apic[LVT_Err] = error.value;
334		340
335	/* Initialize LVT LINT0 register. */	341	/* Initialize LVT LINT0 register. */
336	lint.value = l_apic[LVT_LINT0];	342	lint.value = l_apic[LVT_LINT0];
337	lint.masked = true;	343	lint.masked = true;
338	l_apic[LVT_LINT0] = lint.value;	344	l_apic[LVT_LINT0] = lint.value;
339		345
340	/* Initialize LVT LINT1 register. */	346	/* Initialize LVT LINT1 register. */
341	lint.value = l_apic[LVT_LINT1];	347	lint.value = l_apic[LVT_LINT1];
342	lint.masked = true;	348	lint.masked = true;
343	l_apic[LVT_LINT1] = lint.value;	349	l_apic[LVT_LINT1] = lint.value;
344		350
345	/* Task Priority Register initialization. */	351	/* Task Priority Register initialization. */
346	tpr.value = l_apic[TPR];	352	tpr.value = l_apic[TPR];
347	tpr.pri_sc = 0;	353	tpr.pri_sc = 0;
348	tpr.pri = 0;	354	tpr.pri = 0;
349	l_apic[TPR] = tpr.value;	355	l_apic[TPR] = tpr.value;
350		356
351	/* Spurious-Interrupt Vector Register initialization. */	357	/* Spurious-Interrupt Vector Register initialization. */
352	svr.value = l_apic[SVR];	358	svr.value = l_apic[SVR];
353	svr.vector = VECTOR_APIC_SPUR;	359	svr.vector = VECTOR_APIC_SPUR;
354	svr.lapic_enabled = true;	360	svr.lapic_enabled = true;
355	svr.focus_checking = true;	361	svr.focus_checking = true;
356	l_apic[SVR] = svr.value;	362	l_apic[SVR] = svr.value;
357		363
358	if (CPU->arch.family >= 6)	364	if (CPU->arch.family >= 6)
359	enable_l_apic_in_msr();	365	enable_l_apic_in_msr();
360		366
361	/* Interrupt Command Register initialization. */	367	/* Interrupt Command Register initialization. */
362	icr.lo = l_apic[ICRlo];	368	icr.lo = l_apic[ICRlo];
363	icr.delmod = DELMOD_INIT;	369	icr.delmod = DELMOD_INIT;
364	icr.destmod = DESTMOD_PHYS;	370	icr.destmod = DESTMOD_PHYS;
365	icr.level = LEVEL_DEASSERT;	371	icr.level = LEVEL_DEASSERT;
366	icr.shorthand = SHORTHAND_ALL_INCL;	372	icr.shorthand = SHORTHAND_ALL_INCL;
367	icr.trigger_mode = TRIGMOD_LEVEL;	373	icr.trigger_mode = TRIGMOD_LEVEL;
368	l_apic[ICRlo] = icr.lo;	374	l_apic[ICRlo] = icr.lo;
369		375
370	/* Timer Divide Configuration Register initialization. */	376	/* Timer Divide Configuration Register initialization. */
371	tdcr.value = l_apic[TDCR];	377	tdcr.value = l_apic[TDCR];
372	tdcr.div_value = DIVIDE_1;	378	tdcr.div_value = DIVIDE_1;
373	l_apic[TDCR] = tdcr.value;	379	l_apic[TDCR] = tdcr.value;
374		380
375	/* Program local timer. */	381	/* Program local timer. */
376	tm.value = l_apic[LVT_Tm];	382	tm.value = l_apic[LVT_Tm];
377	tm.vector = VECTOR_CLK;	383	tm.vector = VECTOR_CLK;
378	tm.mode = TIMER_PERIODIC;	384	tm.mode = TIMER_PERIODIC;
379	tm.masked = false;	385	tm.masked = false;
380	l_apic[LVT_Tm] = tm.value;	386	l_apic[LVT_Tm] = tm.value;
381		387
382	/*	388	/*
383	* Measure and configure the timer to generate timer	389	* Measure and configure the timer to generate timer
384	* interrupt with period 1s/HZ seconds.	390	* interrupt with period 1s/HZ seconds.
385	*/	391	*/
386	t1 = l_apic[CCRT];	392	t1 = l_apic[CCRT];
387	l_apic[ICRT] = 0xffffffff;	393	l_apic[ICRT] = 0xffffffff;
388		394
389	while (l_apic[CCRT] == t1)	395	while (l_apic[CCRT] == t1)
390	;	396	;
391		397
392	t1 = l_apic[CCRT];	398	t1 = l_apic[CCRT];
393	delay(1000000/HZ);	399	delay(1000000/HZ);
394	t2 = l_apic[CCRT];	400	t2 = l_apic[CCRT];
395		401
396	l_apic[ICRT] = t1-t2;	402	l_apic[ICRT] = t1-t2;
397		403
398	/* Program Logical Destination Register. */	404	/* Program Logical Destination Register. */
399	ldr.value = l_apic[LDR];	405	ldr.value = l_apic[LDR];
400	if (CPU->id < sizeof(CPU->id)8) / size in bits */	406	if (CPU->id < sizeof(CPU->id)8) / size in bits */
401	ldr.id = (1<<CPU->id);	407	ldr.id = (1<<CPU->id);
402	l_apic[LDR] = ldr.value;	408	l_apic[LDR] = ldr.value;
403		409
404	/* Program Destination Format Register for Flat mode. */	410	/* Program Destination Format Register for Flat mode. */
405	dfr.value = l_apic[DFR];	411	dfr.value = l_apic[DFR];
406	dfr.model = MODEL_FLAT;	412	dfr.model = MODEL_FLAT;
407	l_apic[DFR] = dfr.value;	413	l_apic[DFR] = dfr.value;
408	}	414	}
409		415
410	/** Local APIC End of Interrupt. */	416	/** Local APIC End of Interrupt. */
411	void l_apic_eoi(void)	417	void l_apic_eoi(void)
412	{	418	{
413	l_apic[EOI] = 0;	419	l_apic[EOI] = 0;
414	}	420	}
415		421
416	/** Dump content of Local APIC registers. */	422	/** Dump content of Local APIC registers. */
417	void l_apic_debug(void)	423	void l_apic_debug(void)
418	{	424	{
419	#ifdef LAPIC_VERBOSE	425	#ifdef LAPIC_VERBOSE
420	lvt_tm_t tm;	426	lvt_tm_t tm;
421	lvt_lint_t lint;	427	lvt_lint_t lint;
422	lvt_error_t error;	428	lvt_error_t error;
423		429
424	printf("LVT on cpu%d, LAPIC ID: %d\n", CPU->id, l_apic_id());	430	printf("LVT on cpu%d, LAPIC ID: %d\n", CPU->id, l_apic_id());
425		431
426	tm.value = l_apic[LVT_Tm];	432	tm.value = l_apic[LVT_Tm];
427	printf("LVT Tm: vector=%hhd, %s, %s, %s\n", tm.vector, delivs_str[tm.delivs], mask_str[tm.masked], tm_mode_str[tm.mode]);	433	printf("LVT Tm: vector=%hhd, %s, %s, %s\n", tm.vector, delivs_str[tm.delivs], mask_str[tm.masked], tm_mode_str[tm.mode]);
428	lint.value = l_apic[LVT_LINT0];	434	lint.value = l_apic[LVT_LINT0];
429	printf("LVT LINT0: vector=%hhd, %s, %s, %s, irr=%d, %s, %s\n", tm.vector, delmod_str[lint.delmod], delivs_str[lint.delivs], intpol_str[lint.intpol], lint.irr, trigmod_str[lint.trigger_mode], mask_str[lint.masked]);	435	printf("LVT LINT0: vector=%hhd, %s, %s, %s, irr=%d, %s, %s\n", tm.vector, delmod_str[lint.delmod], delivs_str[lint.delivs], intpol_str[lint.intpol], lint.irr, trigmod_str[lint.trigger_mode], mask_str[lint.masked]);
430	lint.value = l_apic[LVT_LINT1];	436	lint.value = l_apic[LVT_LINT1];
431	printf("LVT LINT1: vector=%hhd, %s, %s, %s, irr=%d, %s, %s\n", tm.vector, delmod_str[lint.delmod], delivs_str[lint.delivs], intpol_str[lint.intpol], lint.irr, trigmod_str[lint.trigger_mode], mask_str[lint.masked]);	437	printf("LVT LINT1: vector=%hhd, %s, %s, %s, irr=%d, %s, %s\n", tm.vector, delmod_str[lint.delmod], delivs_str[lint.delivs], intpol_str[lint.intpol], lint.irr, trigmod_str[lint.trigger_mode], mask_str[lint.masked]);
432	error.value = l_apic[LVT_Err];	438	error.value = l_apic[LVT_Err];
433	printf("LVT Err: vector=%hhd, %s, %s\n", error.vector, delivs_str[error.delivs], mask_str[error.masked]);	439	printf("LVT Err: vector=%hhd, %s, %s\n", error.vector, delivs_str[error.delivs], mask_str[error.masked]);
434	#endif	440	#endif
435	}	441	}
436		442
437	/** Local APIC Timer Interrupt.	443	/** Local APIC Timer Interrupt.
438	*	444	*
439	* @param n Interrupt vector number.	445	* @param n Interrupt vector number.
440	* @param stack Interrupted stack.	446	* @param stack Interrupted stack.
441	*/	447	*/
442	void l_apic_timer_interrupt(int n, istate_t *istate)	448	void l_apic_timer_interrupt(int n, istate_t *istate)
443	{	449	{
444	l_apic_eoi();	450	l_apic_eoi();
445	clock();	451	clock();
446	}	452	}
447		453
448	/** Get Local APIC ID.	454	/** Get Local APIC ID.
449	*	455	*
450	* @return Local APIC ID.	456	* @return Local APIC ID.
451	*/	457	*/
452	__u8 l_apic_id(void)	458	__u8 l_apic_id(void)
453	{	459	{
454	l_apic_id_t idreg;	460	l_apic_id_t idreg;
455		461
456	idreg.value = l_apic[L_APIC_ID];	462	idreg.value = l_apic[L_APIC_ID];
457	return idreg.apic_id;	463	return idreg.apic_id;
458	}	464	}
459		465
460	/** Read from IO APIC register.	466	/** Read from IO APIC register.
461	*	467	*
462	* @param address IO APIC register address.	468	* @param address IO APIC register address.
463	*	469	*
464	* @return Content of the addressed IO APIC register.	470	* @return Content of the addressed IO APIC register.
465	*/	471	*/
466	__u32 io_apic_read(__u8 address)	472	__u32 io_apic_read(__u8 address)
467	{	473	{
468	io_regsel_t regsel;	474	io_regsel_t regsel;
469		475
470	regsel.value = io_apic[IOREGSEL];	476	regsel.value = io_apic[IOREGSEL];
471	regsel.reg_addr = address;	477	regsel.reg_addr = address;
472	io_apic[IOREGSEL] = regsel.value;	478	io_apic[IOREGSEL] = regsel.value;
473	return io_apic[IOWIN];	479	return io_apic[IOWIN];
474	}	480	}
475		481
476	/** Write to IO APIC register.	482	/** Write to IO APIC register.
477	*	483	*
478	* @param address IO APIC register address.	484	* @param address IO APIC register address.
479	* @param Content to be written to the addressed IO APIC register.	485	* @param Content to be written to the addressed IO APIC register.
480	*/	486	*/
481	void io_apic_write(__u8 address, __u32 x)	487	void io_apic_write(__u8 address, __u32 x)
482	{	488	{
483	io_regsel_t regsel;	489	io_regsel_t regsel;
484		490
485	regsel.value = io_apic[IOREGSEL];	491	regsel.value = io_apic[IOREGSEL];
486	regsel.reg_addr = address;	492	regsel.reg_addr = address;
487	io_apic[IOREGSEL] = regsel.value;	493	io_apic[IOREGSEL] = regsel.value;
488	io_apic[IOWIN] = x;	494	io_apic[IOWIN] = x;
489	}	495	}
490		496
491	/** Change some attributes of one item in I/O Redirection Table.	497	/** Change some attributes of one item in I/O Redirection Table.
492	*	498	*
493	* @param pin IO APIC pin number.	499	* @param pin IO APIC pin number.
494	* @param dest Interrupt destination address.	500	* @param dest Interrupt destination address.

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(root)/kernel/trunk/arch/ia32/src/smp/apic.c – Rev 1684 → 1702