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| Rev 195 | Rev 232 | ||
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| Line 163... | Line 163... | ||
| 163 | 163 | ||
| 164 | void pm_init(void) |
164 | void pm_init(void) |
| 165 | { |
165 | { |
| 166 | struct descriptor *gdt_p = (struct descriptor *) PA2KA(gdtr.base); |
166 | struct descriptor *gdt_p = (struct descriptor *) PA2KA(gdtr.base); |
| 167 | 167 | ||
| - | 168 | ||
| - | 169 | /* |
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| - | 170 | * Update addresses in GDT and IDT to their virtual counterparts. |
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| - | 171 | */ |
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| - | 172 | gdtr.base = KA2PA(gdtr.base); |
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| - | 173 | idtr.base = (__address) idt; |
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| - | 174 | __asm__ volatile ("lgdt %0\n" : : "m" (gdtr)); |
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| - | 175 | __asm__ volatile ("lidt %0\n" : : "m" (idtr)); |
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| - | 176 | ||
| 168 | /* |
177 | /* |
| 169 | * Each CPU has its private GDT and TSS. |
178 | * Each CPU has its private GDT and TSS. |
| 170 | * All CPUs share one IDT. |
179 | * All CPUs share one IDT. |
| 171 | */ |
180 | */ |
| 172 | 181 | ||
| Line 195... | Line 204... | ||
| 195 | 204 | ||
| 196 | /* |
205 | /* |
| 197 | * As of this moment, the current CPU has its own GDT pointing |
206 | * As of this moment, the current CPU has its own GDT pointing |
| 198 | * to its own TSS. We just need to load the TR register. |
207 | * to its own TSS. We just need to load the TR register. |
| 199 | */ |
208 | */ |
| 200 | __asm__("ltr %0" : : "r" ((__u16) selector(TSS_DES))); |
209 | __asm__ volatile ("ltr %0" : : "r" ((__u16) selector(TSS_DES))); |
| 201 | 210 | ||
| 202 | clean_IOPL_NT_flags(); /* Disable I/O on nonprivileged levels */ |
211 | clean_IOPL_NT_flags(); /* Disable I/O on nonprivileged levels */ |
| 203 | clean_AM_flag(); /* Disable alignment check */ |
212 | clean_AM_flag(); /* Disable alignment check */ |
| 204 | } |
213 | } |