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Rev 15 Rev 125
Line 81... Line 81...
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    outb(CLK_PORT4, 0x30);
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    outb(CLK_PORT4, 0x30);
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    outb(CLK_PORT1, 0xff);
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    outb(CLK_PORT1, 0xff);
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    outb(CLK_PORT1, 0xff);
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    outb(CLK_PORT1, 0xff);
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    do {
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    do {
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            /* will read both status and count */
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        /* will read both status and count */
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        outb(CLK_PORT4, 0xc2);
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        outb(CLK_PORT4, 0xc2);
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        not_ok = (inb(CLK_PORT1)>>6)&1;
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        not_ok = (inb(CLK_PORT1)>>6)&1;
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        t1 = inb(CLK_PORT1);
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        t1 = inb(CLK_PORT1);
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        t1 |= inb(CLK_PORT1) << 8;
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        t1 |= inb(CLK_PORT1) << 8;
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    } while (not_ok);
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    } while (not_ok);
Line 107... Line 107...
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    outb(CLK_PORT4, 0xd2);
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    outb(CLK_PORT4, 0xd2);
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    o2 = inb(CLK_PORT1);
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    o2 = inb(CLK_PORT1);
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    o2 |= inb(CLK_PORT1) << 8;
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    o2 |= inb(CLK_PORT1) << 8;
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 - 
 
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    CPU->delay_loop_const = ((MAGIC_NUMBER*LOOPS)/1000) / ((t1-t2)-(o1-o2)) +
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    CPU->delay_loop_const = ((MAGIC_NUMBER*LOOPS)/1000) / ((t1-t2)-(o1-o2)) + (((MAGIC_NUMBER*LOOPS)/1000) % ((t1-t2)-(o1-o2)) ? 1 : 0);
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                    (((MAGIC_NUMBER*LOOPS)/1000) % ((t1-t2)-(o1-o2)) ? 1 : 0);
 - 
 
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 - 
 
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    clk1 = rdtsc();
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    clk1 = rdtsc();
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    delay(1<<SHIFT);
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    delay(1<<SHIFT);
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    clk2 = rdtsc();
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    clk2 = rdtsc();
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