WebSVN – HelenOS-historic – Diff – /kernel/trunk/arch/ia32/src/asm.S


#
# Copyright (C) 2001-2004 Jakub Jermar
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions
# are met:
#
# - Redistributions of source code must retain the above copyright
#   notice, this list of conditions and the following disclaimer.
# - Redistributions in binary form must reproduce the above copyright
#   notice, this list of conditions and the following disclaimer in the
#   documentation and/or other materials provided with the distribution.
# - The name of the author may not be used to endorse or promote products
#   derived from this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
 
## very low and hardware-level functions
 
# Mask for interrupts 0 - 31 (bits 0 - 31) where 0 means that int has no error word
# and 1 means interrupt with error word
#define ERROR_WORD_INTERRUPT_LIST 0x00027D00
 
.text
 
.global paging_on
.global enable_l_apic_in_msr
.global interrupt_handlers
 
## Turn paging on
#
# Enable paging and write-back caching in CR0.
#
paging_on:
	movl %cr0,%edx
	orl $(1<<31),%edx		# paging on
	andl $~((1<<30)|(1<<29)),%edx	# clear Cache Disable and not Write Though
	movl %edx,%cr0
	jmp 0f
0:
	ret
 
 
## Enable local APIC
#
# Enable local APIC in MSR.
#
enable_l_apic_in_msr:
	push %eax
 
	movl $0x1b, %ecx
	rdmsr
	orl $(1<<11),%eax
	orl $(0xfee00000),%eax
	wrmsr
 
	pop %eax
	ret
 
 
## Declare interrupt handlers
#
# Declare interrupt handlers for n interrupt
# vectors starting at vector i.
#
# The handlers setup data segment registers
# and call exc_dispatch().
#
.macro handler i n
	push %ebp
	movl %esp,%ebp
	pusha
 
	push %ds
	push %es
 
	# we must fill the data segment registers
	movw $16,%ax
	movw %ax,%ds
	movw %ax,%es
 
	movl $(\i),%edi
	pushl %ebp
	addl $4,(%esp)
	pushl %edi
	call exc_dispatch
	addl $8,%esp
 
	pop %es
	pop %ds
 
 
# CLNT
	pushfl
	pop %eax
	and $0xFFFFBFFF,%eax
	push %eax
	popfl
	
 
 
# Test if this is interrupt with error word or not
	mov $\i,%cl
	movl $1,%eax
	test $0xe0,%cl
	jnz 0f
	and $0x1f,%cl
	shl %cl,%eax
	and $ERROR_WORD_INTERRUPT_LIST,%eax
	jz 0f
 
 
# Return with error word
	popa
	pop %ebp
	add $4,%esp	# Skip error word
	iret
 
0:
# Return with no error word
	popa
	pop %ebp
	iret
 
	.if (\n-\i)-1
	handler "(\i+1)",\n
	.endif
.endm
 
# keep in sync with pm.h !!!
IDT_ITEMS=64
interrupt_handlers:
h_start:
	handler 0 64
#	handler 64 128	
#	handler 128 192
#	handler 192 256
h_end:
 
.data
.global interrupt_handler_size
 
interrupt_handler_size: .long (h_end-h_start)/IDT_ITEMS
 

Rev 717	Rev 952
1	#	1	#
2	# Copyright (C) 2001-2004 Jakub Jermar	2	# Copyright (C) 2001-2004 Jakub Jermar
3	# All rights reserved.	3	# All rights reserved.
4	#	4	#
5	# Redistribution and use in source and binary forms, with or without	5	# Redistribution and use in source and binary forms, with or without
6	# modification, are permitted provided that the following conditions	6	# modification, are permitted provided that the following conditions
7	# are met:	7	# are met:
8	#	8	#
9	# - Redistributions of source code must retain the above copyright	9	# - Redistributions of source code must retain the above copyright
10	# notice, this list of conditions and the following disclaimer.	10	# notice, this list of conditions and the following disclaimer.
11	# - Redistributions in binary form must reproduce the above copyright	11	# - Redistributions in binary form must reproduce the above copyright
12	# notice, this list of conditions and the following disclaimer in the	12	# notice, this list of conditions and the following disclaimer in the
13	# documentation and/or other materials provided with the distribution.	13	# documentation and/or other materials provided with the distribution.
14	# - The name of the author may not be used to endorse or promote products	14	# - The name of the author may not be used to endorse or promote products
15	# derived from this software without specific prior written permission.	15	# derived from this software without specific prior written permission.
16	#	16	#
17	# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	17	# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18	# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	18	# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19	# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	19	# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20	# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	20	# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21	# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	21	# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22	# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	22	# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23	# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	23	# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24	# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	24	# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25	# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	25	# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26	# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	26	# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27	#	27	#
28		28
29	## very low and hardware-level functions	29	## very low and hardware-level functions
30		30
31	# Mask for interrupts 0 - 31 (bits 0 - 31) where 0 means that int has no error word	31	# Mask for interrupts 0 - 31 (bits 0 - 31) where 0 means that int has no error word
32	# and 1 means interrupt with error word	32	# and 1 means interrupt with error word
33	#define ERROR_WORD_INTERRUPT_LIST 0x00027D00	33	#define ERROR_WORD_INTERRUPT_LIST 0x00027D00
34		34
35	.text	35	.text
36		36
37	.global paging_on	37	.global paging_on
38	.global enable_l_apic_in_msr	38	.global enable_l_apic_in_msr
39	.global interrupt_handlers	39	.global interrupt_handlers
40		40
41	## Turn paging on	41	## Turn paging on
42	#	42	#
43	# Enable paging and write-back caching in CR0.	43	# Enable paging and write-back caching in CR0.
44	#	44	#
45	paging_on:	45	paging_on:
46	movl %cr0,%edx	46	movl %cr0,%edx
47	orl $(1<<31),%edx # paging on	47	orl $(1<<31),%edx # paging on
48	andl $~((1<<30)\|(1<<29)),%edx # clear Cache Disable and not Write Though	48	andl $~((1<<30)\|(1<<29)),%edx # clear Cache Disable and not Write Though
49	movl %edx,%cr0	49	movl %edx,%cr0
50	jmp 0f	50	jmp 0f
51	0:	51	0:
52	ret	52	ret
53		53
54		54
55	## Enable local APIC	55	## Enable local APIC
56	#	56	#
57	# Enable local APIC in MSR.	57	# Enable local APIC in MSR.
58	#	58	#
59	enable_l_apic_in_msr:	59	enable_l_apic_in_msr:
60	push %eax	60	push %eax
61		61
62	movl $0x1b, %ecx	62	movl $0x1b, %ecx
63	rdmsr	63	rdmsr
64	orl $(1<<11),%eax	64	orl $(1<<11),%eax
65	orl $(0xfee00000),%eax	65	orl $(0xfee00000),%eax
66	wrmsr	66	wrmsr
67		67
68	pop %eax	68	pop %eax
69	ret	69	ret
70		70
71		71
72	## Declare interrupt handlers	72	## Declare interrupt handlers
73	#	73	#
74	# Declare interrupt handlers for n interrupt	74	# Declare interrupt handlers for n interrupt
75	# vectors starting at vector i.	75	# vectors starting at vector i.
76	#	76	#
77	# The handlers setup data segment registers	77	# The handlers setup data segment registers
78	# and call exc_dispatch().	78	# and call exc_dispatch().
79	#	79	#
80	.macro handler i n	80	.macro handler i n
81	push %ebp	81	push %ebp
82	movl %esp,%ebp	82	movl %esp,%ebp
83	pusha	83	pusha
84		84
85	push %ds	85	push %ds
86	push %es	86	push %es
87		87
88	# we must fill the data segment registers	88	# we must fill the data segment registers
89	movw $16,%ax	89	movw $16,%ax
90	movw %ax,%ds	90	movw %ax,%ds
91	movw %ax,%es	91	movw %ax,%es
92		92
93	movl $(\i),%edi	93	movl $(\i),%edi
94	pushl %ebp	94	pushl %ebp
95	addl $4,(%esp)	95	addl $4,(%esp)
96	pushl %edi	96	pushl %edi
97	call exc_dispatch	97	call exc_dispatch
98	addl $8,%esp	98	addl $8,%esp
99		99
100	pop %es	100	pop %es
101	pop %ds	101	pop %ds
102		102
103		103
104	# CLNT	104	# CLNT
105	pushfl	105	pushfl
106	pop %eax	106	pop %eax
107	and $0xFFFFBFFF,%eax	107	and $0xFFFFBFFF,%eax
108	push %eax	108	push %eax
109	popfl	109	popfl
110		110
111		111
112		112
113	# Test if this is interrupt with error word or not	113	# Test if this is interrupt with error word or not
114	mov $\i,%cl	114	mov $\i,%cl
115	movl $1,%eax	115	movl $1,%eax
116	test $0xe0,%cl	116	test $0xe0,%cl
117	jnz 0f	117	jnz 0f
118	and $0x1f,%cl	118	and $0x1f,%cl
119	shl %cl,%eax	119	shl %cl,%eax
120	and $ERROR_WORD_INTERRUPT_LIST,%eax	120	and $ERROR_WORD_INTERRUPT_LIST,%eax
121	jz 0f	121	jz 0f
122		122
123		123
124	# Return with error word	124	# Return with error word
125	popa	125	popa
126	pop %ebp	126	pop %ebp
127	add $4,%esp # Skip error word	127	add $4,%esp # Skip error word
128	iret	128	iret
129		129
130	0:	130	0:
131	# Return with no error word	131	# Return with no error word
132	popa	132	popa
133	pop %ebp	133	pop %ebp
134	iret	134	iret
135		135
136	.if (\n-\i)-1	136	.if (\n-\i)-1
137	handler "(\i+1)",\n	137	handler "(\i+1)",\n
138	.endif	138	.endif
139	.endm	139	.endm
140		140
141	# keep in sync with pm.h !!!	141	# keep in sync with pm.h !!!
142	IDT_ITEMS=64	142	IDT_ITEMS=64
143	interrupt_handlers:	143	interrupt_handlers:
144	h_start:	144	h_start:
145	handler 0 64	145	handler 0 64
146	# handler 64 128	146	# handler 64 128
147	# handler 128 192	147	# handler 128 192
148	# handler 192 256	148	# handler 192 256
149	h_end:	149	h_end:
150		150
151	.data	151	.data
152	.global interrupt_handler_size	152	.global interrupt_handler_size
153		153
154	interrupt_handler_size: .long (h_end-h_start)/IDT_ITEMS	154	interrupt_handler_size: .long (h_end-h_start)/IDT_ITEMS
155		155

Subversion Repositories HelenOS-historic

(root)/kernel/trunk/arch/ia32/src/asm.S – Rev 717 → 952