WebSVN – HelenOS-historic – Diff – /kernel/trunk/arch/ia32/include/atomic.h


/*
 * Copyright (C) 2001-2004 Jakub Jermar
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * - Redistributions of source code must retain the above copyright
 *   notice, this list of conditions and the following disclaimer.
 * - Redistributions in binary form must reproduce the above copyright
 *   notice, this list of conditions and the following disclaimer in the
 *   documentation and/or other materials provided with the distribution.
 * - The name of the author may not be used to endorse or promote products
 *   derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
#ifndef __ia32_ATOMIC_H__
#define __ia32_ATOMIC_H__
 
#include <arch/types.h>
#include <arch/barrier.h>
#include <preemption.h>
#include <typedefs.h>
 
static inline void atomic_inc(atomic_t *val) {
#ifdef CONFIG_SMP
    __asm__ volatile ("lock incl %0\n" : "=m" (val->count));
#else
    __asm__ volatile ("incl %0\n" : "=m" (val->count));
#endif /* CONFIG_SMP */
}
 
static inline void atomic_dec(atomic_t *val) {
#ifdef CONFIG_SMP
    __asm__ volatile ("lock decl %0\n" : "=m" (val->count));
#else
    __asm__ volatile ("decl %0\n" : "=m" (val->count));
#endif /* CONFIG_SMP */
}
 
static inline long atomic_postinc(atomic_t *val)
{
    long r = 1;
 
    __asm__ volatile (
        "lock xaddl %1, %0\n"
        : "=m" (val->count), "+r" (r)
    );
 
    return r;
}
 
static inline long atomic_postdec(atomic_t *val)
{
    long r = -1;
   
    __asm__ volatile (
        "lock xaddl %1, %0\n"
        : "=m" (val->count), "+r"(r)
    );
   
    return r;
}
 
#define atomic_preinc(val) (atomic_postinc(val)+1)
#define atomic_predec(val) (atomic_postdec(val)-1)
 
static inline __u32 test_and_set(atomic_t *val) {
    __u32 v;
   
    __asm__ volatile (
        "movl $1, %0\n"
        "xchgl %0, %1\n"
        : "=r" (v),"=m" (val->count)
    );
   
    return v;
}
 
/** ia32 specific fast spinlock */
static inline void atomic_lock_arch(atomic_t *val)
{
    __u32 tmp;
 
    preemption_disable();
    __asm__ volatile (
        "0:;"
#ifdef CONFIG_HT
        "pause;" /* Pentium 4's HT love this instruction */
#endif
        "mov %0, %1;"
        "testl %1, %1;"
        "jnz 0b;"       /* Lightweight looping on locked spinlock */
       
        "incl %1;"      /* now use the atomic operation */
        "xchgl %0, %1;"
        "testl %1, %1;"
        "jnz 0b;"
                : "=m"(val->count),"=r"(tmp)
        );
    /*
     * Prevent critical section code from bleeding out this way up.
     */
    CS_ENTER_BARRIER();
}
 
#endif
 

Rev 1691	Rev 1697
1	/*	1	/*
2	* Copyright (C) 2001-2004 Jakub Jermar	2	* Copyright (C) 2001-2004 Jakub Jermar
3	* All rights reserved.	3	* All rights reserved.
4	*	4	*
5	* Redistribution and use in source and binary forms, with or without	5	* Redistribution and use in source and binary forms, with or without
6	* modification, are permitted provided that the following conditions	6	* modification, are permitted provided that the following conditions
7	* are met:	7	* are met:
8	*	8	*
9	* - Redistributions of source code must retain the above copyright	9	* - Redistributions of source code must retain the above copyright
10	* notice, this list of conditions and the following disclaimer.	10	* notice, this list of conditions and the following disclaimer.
11	* - Redistributions in binary form must reproduce the above copyright	11	* - Redistributions in binary form must reproduce the above copyright
12	* notice, this list of conditions and the following disclaimer in the	12	* notice, this list of conditions and the following disclaimer in the
13	* documentation and/or other materials provided with the distribution.	13	* documentation and/or other materials provided with the distribution.
14	* - The name of the author may not be used to endorse or promote products	14	* - The name of the author may not be used to endorse or promote products
15	* derived from this software without specific prior written permission.	15	* derived from this software without specific prior written permission.
16	*	16	*
17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27	*/	27	*/
28		28
29	#ifndef __ia32_ATOMIC_H__	29	#ifndef __ia32_ATOMIC_H__
30	#define __ia32_ATOMIC_H__	30	#define __ia32_ATOMIC_H__
31		31
32	#include <arch/types.h>	32	#include <arch/types.h>
33	#include <arch/barrier.h>	33	#include <arch/barrier.h>
34	#include <preemption.h>	34	#include <preemption.h>
35	#include <typedefs.h>	35	#include <typedefs.h>
36		36
37	static inline void atomic_inc(atomic_t *val) {	37	static inline void atomic_inc(atomic_t *val) {
38	#ifdef CONFIG_SMP	38	#ifdef CONFIG_SMP
39	__asm__ volatile ("lock incl %0\n" : "=m" (val->count));	39	__asm__ volatile ("lock incl %0\n" : "=m" (val->count));
40	#else	40	#else
41	__asm__ volatile ("incl %0\n" : "=m" (val->count));	41	__asm__ volatile ("incl %0\n" : "=m" (val->count));
42	#endif /* CONFIG_SMP */	42	#endif /* CONFIG_SMP */
43	}	43	}
44		44
45	static inline void atomic_dec(atomic_t *val) {	45	static inline void atomic_dec(atomic_t *val) {
46	#ifdef CONFIG_SMP	46	#ifdef CONFIG_SMP
47	__asm__ volatile ("lock decl %0\n" : "=m" (val->count));	47	__asm__ volatile ("lock decl %0\n" : "=m" (val->count));
48	#else	48	#else
49	__asm__ volatile ("decl %0\n" : "=m" (val->count));	49	__asm__ volatile ("decl %0\n" : "=m" (val->count));
50	#endif /* CONFIG_SMP */	50	#endif /* CONFIG_SMP */
51	}	51	}
52		52
53	static inline long atomic_postinc(atomic_t *val)	53	static inline long atomic_postinc(atomic_t *val)
54	{	54	{
55	long r = 1;	55	long r = 1;
56		56
57	__asm__ volatile (	57	__asm__ volatile (
58	"lock xaddl %1, %0\n"	58	"lock xaddl %1, %0\n"
59	: "=m" (val->count) : "r" (r)	59	: "=m" (val->count), "+r" (r)
60	);	60	);
61		61
62	return r;	62	return r;
63	}	63	}
64		64
65	static inline long atomic_postdec(atomic_t *val)	65	static inline long atomic_postdec(atomic_t *val)
66	{	66	{
67	long r = -1;	67	long r = -1;
68		68
69	__asm__ volatile (	69	__asm__ volatile (
70	"lock xaddl %1, %0\n"	70	"lock xaddl %1, %0\n"
71	: "=m" (val->count) : "r"(r)	71	: "=m" (val->count), "+r"(r)
72	);	72	);
73		73
74	return r;	74	return r;
75	}	75	}
76		76
77	#define atomic_preinc(val) (atomic_postinc(val)+1)	77	#define atomic_preinc(val) (atomic_postinc(val)+1)
78	#define atomic_predec(val) (atomic_postdec(val)-1)	78	#define atomic_predec(val) (atomic_postdec(val)-1)
79		79
80	static inline __u32 test_and_set(atomic_t *val) {	80	static inline __u32 test_and_set(atomic_t *val) {
81	__u32 v;	81	__u32 v;
82		82
83	__asm__ volatile (	83	__asm__ volatile (
84	"movl $1, %0\n"	84	"movl $1, %0\n"
85	"xchgl %0, %1\n"	85	"xchgl %0, %1\n"
86	: "=r" (v),"=m" (val->count)	86	: "=r" (v),"=m" (val->count)
87	);	87	);
88		88
89	return v;	89	return v;
90	}	90	}
91		91
92	/** ia32 specific fast spinlock */	92	/** ia32 specific fast spinlock */
93	static inline void atomic_lock_arch(atomic_t *val)	93	static inline void atomic_lock_arch(atomic_t *val)
94	{	94	{
95	__u32 tmp;	95	__u32 tmp;
96		96
97	preemption_disable();	97	preemption_disable();
98	__asm__ volatile (	98	__asm__ volatile (
99	"0:;"	99	"0:;"
100	#ifdef CONFIG_HT	100	#ifdef CONFIG_HT
101	"pause;" /* Pentium 4's HT love this instruction */	101	"pause;" /* Pentium 4's HT love this instruction */
102	#endif	102	#endif
103	"mov %0, %1;"	103	"mov %0, %1;"
104	"testl %1, %1;"	104	"testl %1, %1;"
105	"jnz 0b;" /* Lightweight looping on locked spinlock */	105	"jnz 0b;" /* Lightweight looping on locked spinlock */
106		106
107	"incl %1;" /* now use the atomic operation */	107	"incl %1;" /* now use the atomic operation */
108	"xchgl %0, %1;"	108	"xchgl %0, %1;"
109	"testl %1, %1;"	109	"testl %1, %1;"
110	"jnz 0b;"	110	"jnz 0b;"
111	: "=m"(val->count),"=r"(tmp)	111	: "=m"(val->count),"=r"(tmp)
112	);	112	);
113	/*	113	/*
114	* Prevent critical section code from bleeding out this way up.	114	* Prevent critical section code from bleeding out this way up.
115	*/	115	*/
116	CS_ENTER_BARRIER();	116	CS_ENTER_BARRIER();
117	}	117	}
118		118
119	#endif	119	#endif
120		120

Subversion Repositories HelenOS-historic

(root)/kernel/trunk/arch/ia32/include/atomic.h – Rev 1691 → 1697