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#include <arch/pm.h>
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#include <arch/pm.h>
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#include <arch/types.h>
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#include <arch/types.h>
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#include <config.h>
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#include <config.h>
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extern __u32 interrupt_handler_size;
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extern uint32_t interrupt_handler_size;
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extern void paging_on(void);
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extern void paging_on(void);
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extern void interrupt_handlers(void);
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extern void interrupt_handlers(void);
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extern void enable_l_apic_in_msr(void);
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extern void enable_l_apic_in_msr(void);
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extern void asm_delay_loop(__u32 t);
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extern void asm_delay_loop(uint32_t t);
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extern void asm_fake_loop(__u32 t);
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extern void asm_fake_loop(uint32_t t);
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/** Halt CPU
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/** Halt CPU
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 *
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 *
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 * Halt the current CPU until interrupt event.
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 * Halt the current CPU until interrupt event.
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 */
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 */
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static inline void cpu_halt(void) { __asm__("hlt\n"); };
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static inline void cpu_halt(void) { __asm__("hlt\n"); };
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static inline void cpu_sleep(void) { __asm__("hlt\n"); };
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static inline void cpu_sleep(void) { __asm__("hlt\n"); };
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#define GEN_READ_REG(reg) static inline __native read_ ##reg (void) \
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#define GEN_READ_REG(reg) static inline unative_t read_ ##reg (void) \
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    { \
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    { \
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    __native res; \
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    unative_t res; \
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    __asm__ volatile ("movl %%" #reg ", %0" : "=r" (res) ); \
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    __asm__ volatile ("movl %%" #reg ", %0" : "=r" (res) ); \
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    return res; \
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    return res; \
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    }
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    }
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#define GEN_WRITE_REG(reg) static inline void write_ ##reg (__native regn) \
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#define GEN_WRITE_REG(reg) static inline void write_ ##reg (unative_t regn) \
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    { \
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    { \
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    __asm__ volatile ("movl %0, %%" #reg : : "r" (regn)); \
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    __asm__ volatile ("movl %0, %%" #reg : : "r" (regn)); \
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    }
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    }
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GEN_READ_REG(cr0);
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GEN_READ_REG(cr0);
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 * Output byte to port
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 * Output byte to port
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 *
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 *
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 * @param port Port to write to
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 * @param port Port to write to
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 * @param val Value to write
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 * @param val Value to write
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 */
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 */
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static inline void outb(__u16 port, __u8 val) { __asm__ volatile ("outb %b0, %w1\n" : : "a" (val), "d" (port) ); }
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static inline void outb(uint16_t port, uint8_t val) { __asm__ volatile ("outb %b0, %w1\n" : : "a" (val), "d" (port) ); }
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/** Word to port
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/** Word to port
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 *
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 *
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 * Output word to port
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 * Output word to port
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 *
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 *
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 * @param port Port to write to
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 * @param port Port to write to
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 * @param val Value to write
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 * @param val Value to write
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 */
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 */
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static inline void outw(__u16 port, __u16 val) { __asm__ volatile ("outw %w0, %w1\n" : : "a" (val), "d" (port) ); }
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static inline void outw(uint16_t port, uint16_t val) { __asm__ volatile ("outw %w0, %w1\n" : : "a" (val), "d" (port) ); }
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/** Double word to port
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/** Double word to port
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 *
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 *
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 * Output double word to port
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 * Output double word to port
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 *
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 *
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 * @param port Port to write to
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 * @param port Port to write to
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 * @param val Value to write
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 * @param val Value to write
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 */
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 */
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static inline void outl(__u16 port, __u32 val) { __asm__ volatile ("outl %l0, %w1\n" : : "a" (val), "d" (port) ); }
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static inline void outl(uint16_t port, uint32_t val) { __asm__ volatile ("outl %l0, %w1\n" : : "a" (val), "d" (port) ); }
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/** Byte from port
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/** Byte from port
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 *
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 *
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 * Get byte from port
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 * Get byte from port
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 *
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 *
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 * @param port Port to read from
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 * @param port Port to read from
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 * @return Value read
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 * @return Value read
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 */
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 */
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static inline __u8 inb(__u16 port) { __u8 val; __asm__ volatile ("inb %w1, %b0 \n" : "=a" (val) : "d" (port) ); return val; }
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static inline uint8_t inb(uint16_t port) { uint8_t val; __asm__ volatile ("inb %w1, %b0 \n" : "=a" (val) : "d" (port) ); return val; }
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/** Word from port
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/** Word from port
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 *
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 *
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 * Get word from port
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 * Get word from port
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 *
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 *
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 * @param port Port to read from
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 * @param port Port to read from
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 * @return Value read
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 * @return Value read
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 */
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 */
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static inline __u16 inw(__u16 port) { __u16 val; __asm__ volatile ("inw %w1, %w0 \n" : "=a" (val) : "d" (port) ); return val; }
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static inline uint16_t inw(uint16_t port) { uint16_t val; __asm__ volatile ("inw %w1, %w0 \n" : "=a" (val) : "d" (port) ); return val; }
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/** Double word from port
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/** Double word from port
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 *
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 *
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 * Get double word from port
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 * Get double word from port
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 *
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 *
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 * @param port Port to read from
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 * @param port Port to read from
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 * @return Value read
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 * @return Value read
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 */
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 */
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static inline __u32 inl(__u16 port) { __u32 val; __asm__ volatile ("inl %w1, %l0 \n" : "=a" (val) : "d" (port) ); return val; }
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static inline uint32_t inl(uint16_t port) { uint32_t val; __asm__ volatile ("inl %w1, %l0 \n" : "=a" (val) : "d" (port) ); return val; }
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/** Enable interrupts.
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/** Enable interrupts.
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 *
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 *
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 * Enable interrupts and return previous
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 * Enable interrupts and return previous
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 * value of EFLAGS.
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 * value of EFLAGS.
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 *
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 *
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 * Return the base address of the current stack.
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 * Return the base address of the current stack.
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 * The stack is assumed to be STACK_SIZE bytes long.
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 * The stack is assumed to be STACK_SIZE bytes long.
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 * The stack must start on page boundary.
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 * The stack must start on page boundary.
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 */
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 */
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static inline __address get_stack_base(void)
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static inline uintptr_t get_stack_base(void)
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{
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{
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    __address v;
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    uintptr_t v;
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    __asm__ volatile ("andl %%esp, %0\n" : "=r" (v) : "0" (~(STACK_SIZE-1)));
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    __asm__ volatile ("andl %%esp, %0\n" : "=r" (v) : "0" (~(STACK_SIZE-1)));
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    return v;
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    return v;
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}
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}
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static inline __u64 rdtsc(void)
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static inline uint64_t rdtsc(void)
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{
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{
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    __u64 v;
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    uint64_t v;
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    __asm__ volatile("rdtsc\n" : "=A" (v));
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    __asm__ volatile("rdtsc\n" : "=A" (v));
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    return v;
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    return v;
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}
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}
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/** Return current IP address */
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/** Return current IP address */
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static inline __address * get_ip()
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static inline uintptr_t * get_ip()
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{
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{
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    __address *ip;
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    uintptr_t *ip;
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    __asm__ volatile (
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    __asm__ volatile (
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        "mov %%eip, %0"
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        "mov %%eip, %0"
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        : "=r" (ip)
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        : "=r" (ip)
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        );
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        );
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/** Invalidate TLB Entry.
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/** Invalidate TLB Entry.
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 *
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 *
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 * @param addr Address on a page whose TLB entry is to be invalidated.
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 * @param addr Address on a page whose TLB entry is to be invalidated.
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 */
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 */
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static inline void invlpg(__address addr)
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static inline void invlpg(uintptr_t addr)
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{
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{
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    __asm__ volatile ("invlpg %0\n" :: "m" (*(__native *)addr));
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    __asm__ volatile ("invlpg %0\n" :: "m" (*(unative_t *)addr));
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}
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}
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/** Load GDTR register from memory.
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/** Load GDTR register from memory.
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 *
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 *
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 * @param gdtr_reg Address of memory from where to load GDTR.
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 * @param gdtr_reg Address of memory from where to load GDTR.
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/** Load TR from descriptor table.
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/** Load TR from descriptor table.
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 *
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 *
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 * @param sel Selector specifying descriptor of TSS segment.
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 * @param sel Selector specifying descriptor of TSS segment.
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 */
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 */
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static inline void tr_load(__u16 sel)
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static inline void tr_load(uint16_t sel)
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{
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{
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    __asm__ volatile ("ltr %0" : : "r" (sel));
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    __asm__ volatile ("ltr %0" : : "r" (sel));
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}
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}
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#endif
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#endif