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| Rev 1187 | Rev 1251 | ||
|---|---|---|---|
| Line 256... | Line 256... | ||
| 256 | * |
256 | * |
| 257 | * @param gdtr_reg Address of memory from where to load GDTR. |
257 | * @param gdtr_reg Address of memory from where to load GDTR. |
| 258 | */ |
258 | */ |
| 259 | static inline void gdtr_load(ptr_16_32_t *gdtr_reg) |
259 | static inline void gdtr_load(ptr_16_32_t *gdtr_reg) |
| 260 | { |
260 | { |
| 261 | __asm__ volatile ("lgdt %0\n" : : "m" (*gdtr_reg)); |
261 | __asm__ volatile ("lgdtl %0\n" : : "m" (*gdtr_reg)); |
| 262 | } |
262 | } |
| 263 | 263 | ||
| 264 | /** Store GDTR register to memory. |
264 | /** Store GDTR register to memory. |
| 265 | * |
265 | * |
| 266 | * @param gdtr_reg Address of memory to where to load GDTR. |
266 | * @param gdtr_reg Address of memory to where to load GDTR. |
| 267 | */ |
267 | */ |
| 268 | static inline void gdtr_store(ptr_16_32_t *gdtr_reg) |
268 | static inline void gdtr_store(ptr_16_32_t *gdtr_reg) |
| 269 | { |
269 | { |
| 270 | __asm__ volatile ("sgdt %0\n" : : "m" (*gdtr_reg)); |
270 | __asm__ volatile ("sgdtl %0\n" : : "m" (*gdtr_reg)); |
| 271 | } |
271 | } |
| 272 | 272 | ||
| 273 | /** Load IDTR register from memory. |
273 | /** Load IDTR register from memory. |
| 274 | * |
274 | * |
| 275 | * @param idtr_reg Address of memory from where to load IDTR. |
275 | * @param idtr_reg Address of memory from where to load IDTR. |
| 276 | */ |
276 | */ |
| 277 | static inline void idtr_load(ptr_16_32_t *idtr_reg) |
277 | static inline void idtr_load(ptr_16_32_t *idtr_reg) |
| 278 | { |
278 | { |
| 279 | __asm__ volatile ("lidt %0\n" : : "m" (*idtr_reg)); |
279 | __asm__ volatile ("lidtl %0\n" : : "m" (*idtr_reg)); |
| 280 | } |
280 | } |
| 281 | 281 | ||
| 282 | /** Load TR from descriptor table. |
282 | /** Load TR from descriptor table. |
| 283 | * |
283 | * |
| 284 | * @param sel Selector specifying descriptor of TSS segment. |
284 | * @param sel Selector specifying descriptor of TSS segment. |