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#include <synch/spinlock.h>
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#include <synch/spinlock.h>
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extern __u32 interrupt_handler_size;
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extern __u32 interrupt_handler_size;
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extern void paging_on(void);
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extern void paging_on(void);
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extern __address cpu_read_dba(void);
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extern void cpu_write_dba(__address dba);
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extern __address cpu_read_cr2(void);
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extern void interrupt_handlers(void);
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extern void interrupt_handlers(void);
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extern __u8 inb(int port);
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extern __u8 inb(int port);
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extern __u16 inw(int port);
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extern __u16 inw(int port);
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extern void outw(int port, __u16 w);
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extern void outw(int port, __u16 w);
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extern void outl(int port, __u32 l);
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extern void outl(int port, __u32 l);
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extern void enable_l_apic_in_msr(void);
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extern void enable_l_apic_in_msr(void);
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/** Halt CPU
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 *
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 * Halt the current CPU until interrupt event.
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 */
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extern void halt_cpu(void);
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static inline void cpu_halt(void) { __asm__("hlt"); };
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extern void cpu_sleep(void);
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static inline void cpu_sleep(void) { __asm__("hlt"); };
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/** Read CR2
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 *
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 * Return value in CR2
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 *
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 * @return Value read.
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 */
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static inline __u32 read_cr2(void) { __u32 v; __asm__ volatile ("movl %%cr2,%0" : "=r" (v)); return v; }
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/** Write CR3
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 *
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 * Write value to CR3.
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 *
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 * @param v Value to be written.
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 */
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static inline void write_dr0(__u32 v);
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static inline void write_cr3(__u32 v) { __asm__ volatile ("movl %0,%%cr3\n" : : "r" (v)); }
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/** Read CR3
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 *
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 * Return value in CR3
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 *
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static inline __u32 read_dr0(void);
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 * @return Value read.
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 */
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static inline __u32 read_cr3(void) { __u32 v; __asm__ volatile ("movl %%cr3,%0" : "=r" (v)); return v; }
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/** Write DR0
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 *
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 * Write value to DR0.
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 *
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 * @param v Value to be written.
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 */
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inline void write_dr0(__u32 v) { __asm__ volatile ("movl %0,%%dr0\n" : : "r" (v)); }
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static inline void write_dr0(__u32 v) { __asm__ volatile ("movl %0,%%dr0\n" : : "r" (v)); }
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/** Read DR0
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 *
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 * Return value in DR0
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 *
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 * @return Value read.
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 */
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inline __u32 read_dr0(void) { __u32 v; __asm__ volatile ("movl %%dr0,%0" : "=r" (v)); return v; }
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static inline __u32 read_dr0(void) { __u32 v; __asm__ volatile ("movl %%dr0,%0" : "=r" (v)); return v; }
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/** Set priority level low
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 *
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 * Enable interrupts and return previous
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 * value of EFLAGS.
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 */
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static inline pri_t cpu_priority_low(void) {
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    pri_t v;
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    __asm__ volatile (
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        "pushf\n"
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        "popl %0\n"
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        "sti\n"
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        : "=r" (v)
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    );
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    return v;
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}
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/** Set priority level high
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 *
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 * Disable interrupts and return previous
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 * value of EFLAGS.
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 */
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static inline pri_t cpu_priority_high(void) {
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    pri_t v;
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    __asm__ volatile (
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        "pushf\n"
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        "popl %0\n"
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        "cli\n"
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        : "=r" (v)
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    );
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    return v;
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}
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/** Restore priority level
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 *
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 * Restore EFLAGS.
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 */
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static inline void cpu_priority_restore(pri_t pri) {
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    __asm__ volatile (
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        "pushl %0\n"
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        "popf\n"
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        : : "r" (pri)
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    );
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}
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/** Return raw priority level
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 *
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 * Return EFLAFS.
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 */
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static inline pri_t cpu_priority_read(void) {
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    pri_t v;
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    __asm__ volatile (
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        "pushf\n"
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        "popl %0\n"
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        : "=r" (v)
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    );
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    return v;
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}
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#endif
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#endif