WebSVN – HelenOS-historic – Diff – /kernel/trunk/arch/amd64/src/pm.c


/*
 * Copyright (C) 2001-2004 Jakub Jermar
 * Copyright (C) 2005-2006 Ondrej Palkovsky
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * - Redistributions of source code must retain the above copyright
 *   notice, this list of conditions and the following disclaimer.
 * - Redistributions in binary form must reproduce the above copyright
 *   notice, this list of conditions and the following disclaimer in the
 *   documentation and/or other materials provided with the distribution.
 * - The name of the author may not be used to endorse or promote products
 *   derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
#include <arch/pm.h>
#include <arch/mm/page.h>
#include <arch/types.h>
#include <arch/interrupt.h>
#include <arch/asm.h>
#include <interrupt.h>
 
#include <config.h>
 
#include <memstr.h>
#include <mm/slab.h>
#include <debug.h>
 
/*
 * There is no segmentation in long mode so we set up flat mode. In this
 * mode, we use, for each privilege level, two segments spanning the
 * whole memory. One is for code and one is for data.
 */
 
struct descriptor gdt[GDT_ITEMS] = {
    /* NULL descriptor */
    { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
    /* KTEXT descriptor */
    { .limit_0_15  = 0xffff,
      .base_0_15   = 0,
      .base_16_23  = 0,
      .access      = AR_PRESENT | AR_CODE | DPL_KERNEL | AR_READABLE ,
      .limit_16_19 = 0xf,
      .available   = 0,
      .longmode    = 1,
      .special     = 0,
      .granularity = 1,
      .base_24_31  = 0 },
    /* KDATA descriptor */
    { .limit_0_15  = 0xffff,
      .base_0_15   = 0,
      .base_16_23  = 0,
      .access      = AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_KERNEL,
      .limit_16_19 = 0xf,
      .available   = 0,
      .longmode    = 0,
      .special     = 0,
      .granularity = 1,
      .base_24_31  = 0 },
    /* UDATA descriptor */
    { .limit_0_15  = 0xffff,
      .base_0_15   = 0,
      .base_16_23  = 0,
      .access      = AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_USER,
      .limit_16_19 = 0xf,
      .available   = 0,
      .longmode    = 0,
      .special     = 1,
      .granularity = 1,
      .base_24_31  = 0 },
    /* UTEXT descriptor */
    { .limit_0_15  = 0xffff,
      .base_0_15   = 0,
      .base_16_23  = 0,
      .access      = AR_PRESENT | AR_CODE | DPL_USER,
      .limit_16_19 = 0xf,
      .available   = 0,
      .longmode    = 1,
      .special     = 0,
      .granularity = 1,
      .base_24_31  = 0 },
    /* KTEXT 32-bit protected, for protected mode before long mode */
    { .limit_0_15  = 0xffff,
      .base_0_15   = 0,
      .base_16_23  = 0,
      .access      = AR_PRESENT | AR_CODE | DPL_KERNEL | AR_READABLE,
      .limit_16_19 = 0xf,
      .available   = 0,
      .longmode    = 0,
      .special     = 1,
      .granularity = 1,
      .base_24_31  = 0 },
    /* TSS descriptor - set up will be completed later,
     * on AMD64 it is 64-bit - 2 items in table */
    { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
    { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
};
 
struct idescriptor idt[IDT_ITEMS];
 
struct ptr_16_64 gdtr = {.limit = sizeof(gdt), .base= (__u64) gdt };
struct ptr_16_64 idtr = {.limit = sizeof(idt), .base= (__u64) idt };
 
static struct tss tss;
struct tss *tss_p = NULL;
 
void gdt_tss_setbase(struct descriptor *d, __address base)
{
    struct tss_descriptor *td = (struct tss_descriptor *) d;
 
    td->base_0_15 = base & 0xffff;
    td->base_16_23 = ((base) >> 16) & 0xff;
    td->base_24_31 = ((base) >> 24) & 0xff;
    td->base_32_63 = ((base) >> 32);
}
 
void gdt_tss_setlimit(struct descriptor *d, __u32 limit)
{
    struct tss_descriptor *td = (struct tss_descriptor *) d;
 
    td->limit_0_15 = limit & 0xffff;
    td->limit_16_19 = (limit >> 16) & 0xf;
}
 
void idt_setoffset(struct idescriptor *d, __address offset)
{
    /*
     * Offset is a linear address.
     */
    d->offset_0_15 = offset & 0xffff;
    d->offset_16_31 = offset >> 16 & 0xffff;
    d->offset_32_63 = offset >> 32;
}
 
void tss_initialize(struct tss *t)
{
    memsetb((__address) t, sizeof(struct tss), 0);
}
 
/*
 * This function takes care of proper setup of IDT and IDTR.
 */
void idt_init(void)
{
    struct idescriptor *d;
    int i;
 
    for (i = 0; i < IDT_ITEMS; i++) {
        d = &idt[i];
 
        d->unused = 0;
        d->selector = gdtselector(KTEXT_DES);
 
        d->present = 1;
        d->type = AR_INTERRUPT; /* masking interrupt */
 
        idt_setoffset(d, ((__address) interrupt_handlers) + i*interrupt_handler_size);
        exc_register(i, "undef", (iroutine)null_interrupt);
    }
    exc_register(13, "gp_fault", gp_fault);
    exc_register( 7, "nm_fault", nm_fault);
    exc_register(12, "ss_fault", ss_fault);
}
 
/** Initialize segmentation - code/data/idt tables
 *
 */
void pm_init(void)
{
    struct descriptor *gdt_p = (struct descriptor *) gdtr.base;
    struct tss_descriptor *tss_desc;
 
    /*
     * Each CPU has its private GDT and TSS.
     * All CPUs share one IDT.
     */
 
    if (config.cpu_active == 1) {
        idt_init();
        /*
         * NOTE: bootstrap CPU has statically allocated TSS, because
         * the heap hasn't been initialized so far.
         */
        tss_p = &tss;
    }
    else {
        tss_p = (struct tss *) malloc(sizeof(struct tss),FRAME_ATOMIC);
        if (!tss_p)
            panic("could not allocate TSS\n");
    }
 
    tss_initialize(tss_p);
 
    tss_desc = (struct tss_descriptor *) (&gdt_p[TSS_DES]);
    tss_desc->present = 1;
    tss_desc->type = AR_TSS;
    tss_desc->dpl = PL_KERNEL;
   
    gdt_tss_setbase(&gdt_p[TSS_DES], (__address) tss_p);
    gdt_tss_setlimit(&gdt_p[TSS_DES], sizeof(struct tss) - 1);
 
    __asm__("lgdt %0" : : "m"(gdtr));
    __asm__("lidt %0" : : "m"(idtr));
    /*
     * As of this moment, the current CPU has its own GDT pointing
     * to its own TSS. We just need to load the TR register.
     */
    __asm__("ltr %0" : : "r" ((__u16) gdtselector(TSS_DES)));
}
 

Rev 814	Rev 822
1	/*	1	/*
2	* Copyright (C) 2001-2004 Jakub Jermar	2	* Copyright (C) 2001-2004 Jakub Jermar
3	* Copyright (C) 2005-2006 Ondrej Palkovsky	3	* Copyright (C) 2005-2006 Ondrej Palkovsky
4	* All rights reserved.	4	* All rights reserved.
5	*	5	*
6	* Redistribution and use in source and binary forms, with or without	6	* Redistribution and use in source and binary forms, with or without
7	* modification, are permitted provided that the following conditions	7	* modification, are permitted provided that the following conditions
8	* are met:	8	* are met:
9	*	9	*
10	* - Redistributions of source code must retain the above copyright	10	* - Redistributions of source code must retain the above copyright
11	* notice, this list of conditions and the following disclaimer.	11	* notice, this list of conditions and the following disclaimer.
12	* - Redistributions in binary form must reproduce the above copyright	12	* - Redistributions in binary form must reproduce the above copyright
13	* notice, this list of conditions and the following disclaimer in the	13	* notice, this list of conditions and the following disclaimer in the
14	* documentation and/or other materials provided with the distribution.	14	* documentation and/or other materials provided with the distribution.
15	* - The name of the author may not be used to endorse or promote products	15	* - The name of the author may not be used to endorse or promote products
16	* derived from this software without specific prior written permission.	16	* derived from this software without specific prior written permission.
17	*	17	*
18	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	18	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	19	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	20	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	21	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	22	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	23	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	24	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	25	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	26	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	27	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28	*/	28	*/
29		29
30	#include <arch/pm.h>	30	#include <arch/pm.h>
31	#include <arch/mm/page.h>	31	#include <arch/mm/page.h>
32	#include <arch/types.h>	32	#include <arch/types.h>
33	#include <arch/interrupt.h>	33	#include <arch/interrupt.h>
34	#include <arch/asm.h>	34	#include <arch/asm.h>
35	#include <interrupt.h>	35	#include <interrupt.h>
36		36
37	#include <config.h>	37	#include <config.h>
38		38
39	#include <memstr.h>	39	#include <memstr.h>
40	#include <mm/slab.h>	40	#include <mm/slab.h>
41	#include <debug.h>	41	#include <debug.h>
42		42
43	/*	43	/*
44	* There is no segmentation in long mode so we set up flat mode. In this	44	* There is no segmentation in long mode so we set up flat mode. In this
45	* mode, we use, for each privilege level, two segments spanning the	45	* mode, we use, for each privilege level, two segments spanning the
46	* whole memory. One is for code and one is for data.	46	* whole memory. One is for code and one is for data.
47	*/	47	*/
48		48
49	struct descriptor gdt[GDT_ITEMS] = {	49	struct descriptor gdt[GDT_ITEMS] = {
50	/* NULL descriptor */	50	/* NULL descriptor */
51	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },	51	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
52	/* KTEXT descriptor */	52	/* KTEXT descriptor */
53	{ .limit_0_15 = 0xffff,	53	{ .limit_0_15 = 0xffff,
54	.base_0_15 = 0,	54	.base_0_15 = 0,
55	.base_16_23 = 0,	55	.base_16_23 = 0,
56	.access = AR_PRESENT \| AR_CODE \| DPL_KERNEL \| AR_READABLE ,	56	.access = AR_PRESENT \| AR_CODE \| DPL_KERNEL \| AR_READABLE ,
57	.limit_16_19 = 0xf,	57	.limit_16_19 = 0xf,
58	.available = 0,	58	.available = 0,
59	.longmode = 1,	59	.longmode = 1,
60	.special = 0,	60	.special = 0,
61	.granularity = 1,	61	.granularity = 1,
62	.base_24_31 = 0 },	62	.base_24_31 = 0 },
63	/* KDATA descriptor */	63	/* KDATA descriptor */
64	{ .limit_0_15 = 0xffff,	64	{ .limit_0_15 = 0xffff,
65	.base_0_15 = 0,	65	.base_0_15 = 0,
66	.base_16_23 = 0,	66	.base_16_23 = 0,
67	.access = AR_PRESENT \| AR_DATA \| AR_WRITABLE \| DPL_KERNEL,	67	.access = AR_PRESENT \| AR_DATA \| AR_WRITABLE \| DPL_KERNEL,
68	.limit_16_19 = 0xf,	68	.limit_16_19 = 0xf,
69	.available = 0,	69	.available = 0,
70	.longmode = 0,	70	.longmode = 0,
71	.special = 0,	71	.special = 0,
72	.granularity = 1,	72	.granularity = 1,
73	.base_24_31 = 0 },	73	.base_24_31 = 0 },
74	/* UDATA descriptor */	74	/* UDATA descriptor */
75	{ .limit_0_15 = 0xffff,	75	{ .limit_0_15 = 0xffff,
76	.base_0_15 = 0,	76	.base_0_15 = 0,
77	.base_16_23 = 0,	77	.base_16_23 = 0,
78	.access = AR_PRESENT \| AR_DATA \| AR_WRITABLE \| DPL_USER,	78	.access = AR_PRESENT \| AR_DATA \| AR_WRITABLE \| DPL_USER,
79	.limit_16_19 = 0xf,	79	.limit_16_19 = 0xf,
80	.available = 0,	80	.available = 0,
81	.longmode = 0,	81	.longmode = 0,
82	.special = 1,	82	.special = 1,
83	.granularity = 1,	83	.granularity = 1,
84	.base_24_31 = 0 },	84	.base_24_31 = 0 },
85	/* UTEXT descriptor */	85	/* UTEXT descriptor */
86	{ .limit_0_15 = 0xffff,	86	{ .limit_0_15 = 0xffff,
87	.base_0_15 = 0,	87	.base_0_15 = 0,
88	.base_16_23 = 0,	88	.base_16_23 = 0,
89	.access = AR_PRESENT \| AR_CODE \| DPL_USER,	89	.access = AR_PRESENT \| AR_CODE \| DPL_USER,
90	.limit_16_19 = 0xf,	90	.limit_16_19 = 0xf,
91	.available = 0,	91	.available = 0,
92	.longmode = 1,	92	.longmode = 1,
93	.special = 0,	93	.special = 0,
94	.granularity = 1,	94	.granularity = 1,
95	.base_24_31 = 0 },	95	.base_24_31 = 0 },
96	/* KTEXT 32-bit protected, for protected mode before long mode */	96	/* KTEXT 32-bit protected, for protected mode before long mode */
97	{ .limit_0_15 = 0xffff,	97	{ .limit_0_15 = 0xffff,
98	.base_0_15 = 0,	98	.base_0_15 = 0,
99	.base_16_23 = 0,	99	.base_16_23 = 0,
100	.access = AR_PRESENT \| AR_CODE \| DPL_KERNEL \| AR_READABLE,	100	.access = AR_PRESENT \| AR_CODE \| DPL_KERNEL \| AR_READABLE,
101	.limit_16_19 = 0xf,	101	.limit_16_19 = 0xf,
102	.available = 0,	102	.available = 0,
103	.longmode = 0,	103	.longmode = 0,
104	.special = 1,	104	.special = 1,
105	.granularity = 1,	105	.granularity = 1,
106	.base_24_31 = 0 },	106	.base_24_31 = 0 },
107	/* TSS descriptor - set up will be completed later,	107	/* TSS descriptor - set up will be completed later,
108	* on AMD64 it is 64-bit - 2 items in table */	108	* on AMD64 it is 64-bit - 2 items in table */
109	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },	109	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
110	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }	110	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
111	};	111	};
112		112
113	struct idescriptor idt[IDT_ITEMS];	113	struct idescriptor idt[IDT_ITEMS];
114		114
115	struct ptr_16_64 gdtr = {.limit = sizeof(gdt), .base= (__u64) gdt };	115	struct ptr_16_64 gdtr = {.limit = sizeof(gdt), .base= (__u64) gdt };
116	struct ptr_16_64 idtr = {.limit = sizeof(idt), .base= (__u64) idt };	116	struct ptr_16_64 idtr = {.limit = sizeof(idt), .base= (__u64) idt };
117		117
118	static struct tss tss;	118	static struct tss tss;
119	struct tss *tss_p = NULL;	119	struct tss *tss_p = NULL;
120		120
121	void gdt_tss_setbase(struct descriptor *d, __address base)	121	void gdt_tss_setbase(struct descriptor *d, __address base)
122	{	122	{
123	struct tss_descriptor td = (struct tss_descriptor ) d;	123	struct tss_descriptor td = (struct tss_descriptor ) d;
124		124
125	td->base_0_15 = base & 0xffff;	125	td->base_0_15 = base & 0xffff;
126	td->base_16_23 = ((base) >> 16) & 0xff;	126	td->base_16_23 = ((base) >> 16) & 0xff;
127	td->base_24_31 = ((base) >> 24) & 0xff;	127	td->base_24_31 = ((base) >> 24) & 0xff;
128	td->base_32_63 = ((base) >> 32);	128	td->base_32_63 = ((base) >> 32);
129	}	129	}
130		130
131	void gdt_tss_setlimit(struct descriptor *d, __u32 limit)	131	void gdt_tss_setlimit(struct descriptor *d, __u32 limit)
132	{	132	{
133	struct tss_descriptor td = (struct tss_descriptor ) d;	133	struct tss_descriptor td = (struct tss_descriptor ) d;
134		134
135	td->limit_0_15 = limit & 0xffff;	135	td->limit_0_15 = limit & 0xffff;
136	td->limit_16_19 = (limit >> 16) & 0xf;	136	td->limit_16_19 = (limit >> 16) & 0xf;
137	}	137	}
138		138
139	void idt_setoffset(struct idescriptor *d, __address offset)	139	void idt_setoffset(struct idescriptor *d, __address offset)
140	{	140	{
141	/*	141	/*
142	* Offset is a linear address.	142	* Offset is a linear address.
143	*/	143	*/
144	d->offset_0_15 = offset & 0xffff;	144	d->offset_0_15 = offset & 0xffff;
145	d->offset_16_31 = offset >> 16 & 0xffff;	145	d->offset_16_31 = offset >> 16 & 0xffff;
146	d->offset_32_63 = offset >> 32;	146	d->offset_32_63 = offset >> 32;
147	}	147	}
148		148
149	void tss_initialize(struct tss *t)	149	void tss_initialize(struct tss *t)
150	{	150	{
151	memsetb((__address) t, sizeof(struct tss), 0);	151	memsetb((__address) t, sizeof(struct tss), 0);
152	}	152	}
153		153
154	/*	154	/*
155	* This function takes care of proper setup of IDT and IDTR.	155	* This function takes care of proper setup of IDT and IDTR.
156	*/	156	*/
157	void idt_init(void)	157	void idt_init(void)
158	{	158	{
159	struct idescriptor *d;	159	struct idescriptor *d;
160	int i;	160	int i;
161		161
162	for (i = 0; i < IDT_ITEMS; i++) {	162	for (i = 0; i < IDT_ITEMS; i++) {
163	d = &idt[i];	163	d = &idt[i];
164		164
165	d->unused = 0;	165	d->unused = 0;
166	d->selector = gdtselector(KTEXT_DES);	166	d->selector = gdtselector(KTEXT_DES);
167		167
168	d->present = 1;	168	d->present = 1;
169	d->type = AR_INTERRUPT; /* masking interrupt */	169	d->type = AR_INTERRUPT; /* masking interrupt */
170		170
171	idt_setoffset(d, ((__address) interrupt_handlers) + i*interrupt_handler_size);	171	idt_setoffset(d, ((__address) interrupt_handlers) + i*interrupt_handler_size);
172	exc_register(i, "undef", (iroutine)null_interrupt);	172	exc_register(i, "undef", (iroutine)null_interrupt);
173	}	173	}
174	exc_register(13, "gp_fault", gp_fault);	174	exc_register(13, "gp_fault", gp_fault);
175	exc_register( 7, "nm_fault", nm_fault);	175	exc_register( 7, "nm_fault", nm_fault);
176	exc_register(12, "ss_fault", ss_fault);	176	exc_register(12, "ss_fault", ss_fault);
177	}	177	}
178		178
179	/** Initialize segmentation - code/data/idt tables	179	/** Initialize segmentation - code/data/idt tables
180	*	180	*
181	*/	181	*/
182	void pm_init(void)	182	void pm_init(void)
183	{	183	{
184	struct descriptor gdt_p = (struct descriptor ) gdtr.base;	184	struct descriptor gdt_p = (struct descriptor ) gdtr.base;
185	struct tss_descriptor *tss_desc;	185	struct tss_descriptor *tss_desc;
186		186
187	/*	187	/*
188	* Each CPU has its private GDT and TSS.	188	* Each CPU has its private GDT and TSS.
189	* All CPUs share one IDT.	189	* All CPUs share one IDT.
190	*/	190	*/
191		191
192	if (config.cpu_active == 1) {	192	if (config.cpu_active == 1) {
193	idt_init();	193	idt_init();
194	/*	194	/*
195	* NOTE: bootstrap CPU has statically allocated TSS, because	195	* NOTE: bootstrap CPU has statically allocated TSS, because
196	* the heap hasn't been initialized so far.	196	* the heap hasn't been initialized so far.
197	*/	197	*/
198	tss_p = &tss;	198	tss_p = &tss;
199	}	199	}
200	else {	200	else {
201	tss_p = (struct tss *) malloc(sizeof(struct tss));	201	tss_p = (struct tss *) malloc(sizeof(struct tss),FRAME_ATOMIC);
202	if (!tss_p)	202	if (!tss_p)
203	panic("could not allocate TSS\n");	203	panic("could not allocate TSS\n");
204	}	204	}
205		205
206	tss_initialize(tss_p);	206	tss_initialize(tss_p);
207		207
208	tss_desc = (struct tss_descriptor *) (&gdt_p[TSS_DES]);	208	tss_desc = (struct tss_descriptor *) (&gdt_p[TSS_DES]);
209	tss_desc->present = 1;	209	tss_desc->present = 1;
210	tss_desc->type = AR_TSS;	210	tss_desc->type = AR_TSS;
211	tss_desc->dpl = PL_KERNEL;	211	tss_desc->dpl = PL_KERNEL;
212		212
213	gdt_tss_setbase(&gdt_p[TSS_DES], (__address) tss_p);	213	gdt_tss_setbase(&gdt_p[TSS_DES], (__address) tss_p);
214	gdt_tss_setlimit(&gdt_p[TSS_DES], sizeof(struct tss) - 1);	214	gdt_tss_setlimit(&gdt_p[TSS_DES], sizeof(struct tss) - 1);
215		215
216	__asm__("lgdt %0" : : "m"(gdtr));	216	__asm__("lgdt %0" : : "m"(gdtr));
217	__asm__("lidt %0" : : "m"(idtr));	217	__asm__("lidt %0" : : "m"(idtr));
218	/*	218	/*
219	* As of this moment, the current CPU has its own GDT pointing	219	* As of this moment, the current CPU has its own GDT pointing
220	* to its own TSS. We just need to load the TR register.	220	* to its own TSS. We just need to load the TR register.
221	*/	221	*/
222	__asm__("ltr %0" : : "r" ((__u16) gdtselector(TSS_DES)));	222	__asm__("ltr %0" : : "r" ((__u16) gdtselector(TSS_DES)));
223	}	223	}
224		224

Subversion Repositories HelenOS-historic

(root)/kernel/trunk/arch/amd64/src/pm.c – Rev 814 → 822