WebSVN – HelenOS-historic – Diff – /kernel/trunk/arch/amd64/src/cpu/cpu.c


/*
 * Copyright (C) 2001-2004 Jakub Jermar
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * - Redistributions of source code must retain the above copyright
 *   notice, this list of conditions and the following disclaimer.
 * - Redistributions in binary form must reproduce the above copyright
 *   notice, this list of conditions and the following disclaimer in the
 *   documentation and/or other materials provided with the distribution.
 * - The name of the author may not be used to endorse or promote products
 *   derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
 /** @addtogroup amd64cpu amd64
 * @ingroup cpu
 * @{
 */
/** @file
 */
 
#include <arch/cpu.h>
#include <arch/cpuid.h>
#include <arch/pm.h>
 
#include <arch.h>
#include <arch/types.h>
#include <print.h>
#include <typedefs.h>
#include <fpu_context.h>
 
/*
 * Identification of CPUs.
 * Contains only non-MP-Specification specific SMP code.
 */
#define AMD_CPUID_EBX   0x68747541
#define AMD_CPUID_ECX   0x444d4163
#define AMD_CPUID_EDX   0x69746e65
 
#define INTEL_CPUID_EBX 0x756e6547
#define INTEL_CPUID_ECX 0x6c65746e
#define INTEL_CPUID_EDX 0x49656e69
 
 
enum vendor {
    VendorUnknown=0,
    VendorAMD,
    VendorIntel
};
 
static char *vendor_str[] = {
    "Unknown Vendor",
    "AuthenticAMD",
    "GenuineIntel"
};
 
 
/** Setup flags on processor so that we can use the FPU
 *
 * cr0.osfxsr = 1 -> we do support fxstor/fxrestor
 * cr0.em = 0 -> we do not emulate coprocessor
 * cr0.mp = 1 -> we do want lazy context switch
 */
void cpu_setup_fpu(void)
{
    __asm__ volatile (
        "movq %%cr0, %%rax;"
        "btsq $1, %%rax;" /* cr0.mp */
        "btrq $2, %%rax;"  /* cr0.em */
        "movq %%rax, %%cr0;"
 
        "movq %%cr4, %%rax;"
        "bts $9, %%rax;" /* cr4.osfxsr */
        "movq %%rax, %%cr4;"
        :
        :
        :"%rax"
        );
}
 
/** Set the TS flag to 1.
 *
 * If a thread accesses coprocessor, exception is run, which
 * does a lazy fpu context switch.
 *
 */
void fpu_disable(void)
{
    __asm__ volatile (
        "mov %%cr0,%%rax;"
        "bts $3,%%rax;"
        "mov %%rax,%%cr0;"
        :
        :
        :"%rax"
        );
}
 
void fpu_enable(void)
{
    __asm__ volatile (
        "mov %%cr0,%%rax;"
        "btr $3,%%rax;"
        "mov %%rax,%%cr0;"
        :
        :
        :"%rax"
        ); 
}
 
void cpu_arch_init(void)
{
    CPU->arch.tss = tss_p;
    CPU->arch.tss->iomap_base = &CPU->arch.tss->iomap[0] - ((__u8 *) CPU->arch.tss);
    CPU->fpu_owner = NULL;
}
 
void cpu_identify(void)
{
    cpu_info_t info;
 
    CPU->arch.vendor = VendorUnknown;
    if (has_cpuid()) {
        cpuid(0, &info);
 
        /*
         * Check for AMD processor.
         */
        if (info.cpuid_ebx==AMD_CPUID_EBX && info.cpuid_ecx==AMD_CPUID_ECX && info.cpuid_edx==AMD_CPUID_EDX) {
            CPU->arch.vendor = VendorAMD;
        }
 
        /*
         * Check for Intel processor.
         */    
        if (info.cpuid_ebx==INTEL_CPUID_EBX && info.cpuid_ecx==INTEL_CPUID_ECX && info.cpuid_edx==INTEL_CPUID_EDX) {
            CPU->arch.vendor = VendorIntel;
        }
               
        cpuid(1, &info);
        CPU->arch.family = (info.cpuid_eax>>8)&0xf;
        CPU->arch.model = (info.cpuid_eax>>4)&0xf;
        CPU->arch.stepping = (info.cpuid_eax>>0)&0xf;                      
    }
}
 
void cpu_print_report(cpu_t* m)
{
    printf("cpu%d: (%s family=%d model=%d stepping=%d) %dMHz\n",
        m->id, vendor_str[m->arch.vendor], m->arch.family, m->arch.model, m->arch.stepping,
        m->frequency_mhz);
}
 
 /** @}
 */
 
 

Rev 1187	Rev 1702
1	/*	1	/*
2	* Copyright (C) 2001-2004 Jakub Jermar	2	* Copyright (C) 2001-2004 Jakub Jermar
3	* All rights reserved.	3	* All rights reserved.
4	*	4	*
5	* Redistribution and use in source and binary forms, with or without	5	* Redistribution and use in source and binary forms, with or without
6	* modification, are permitted provided that the following conditions	6	* modification, are permitted provided that the following conditions
7	* are met:	7	* are met:
8	*	8	*
9	* - Redistributions of source code must retain the above copyright	9	* - Redistributions of source code must retain the above copyright
10	* notice, this list of conditions and the following disclaimer.	10	* notice, this list of conditions and the following disclaimer.
11	* - Redistributions in binary form must reproduce the above copyright	11	* - Redistributions in binary form must reproduce the above copyright
12	* notice, this list of conditions and the following disclaimer in the	12	* notice, this list of conditions and the following disclaimer in the
13	* documentation and/or other materials provided with the distribution.	13	* documentation and/or other materials provided with the distribution.
14	* - The name of the author may not be used to endorse or promote products	14	* - The name of the author may not be used to endorse or promote products
15	* derived from this software without specific prior written permission.	15	* derived from this software without specific prior written permission.
16	*	16	*
17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27	*/	27	*/
28		28
-		29	/** @addtogroup amd64cpu amd64
-		30	* @ingroup cpu
-		31	* @{
-		32	*/
-		33	/** @file
-		34	*/
-		35
29	#include <arch/cpu.h>	36	#include <arch/cpu.h>
30	#include <arch/cpuid.h>	37	#include <arch/cpuid.h>
31	#include <arch/pm.h>	38	#include <arch/pm.h>
32		39
33	#include <arch.h>	40	#include <arch.h>
34	#include <arch/types.h>	41	#include <arch/types.h>
35	#include <print.h>	42	#include <print.h>
36	#include <typedefs.h>	43	#include <typedefs.h>
37	#include <fpu_context.h>	44	#include <fpu_context.h>
38		45
39	/*	46	/*
40	* Identification of CPUs.	47	* Identification of CPUs.
41	* Contains only non-MP-Specification specific SMP code.	48	* Contains only non-MP-Specification specific SMP code.
42	*/	49	*/
43	#define AMD_CPUID_EBX 0x68747541	50	#define AMD_CPUID_EBX 0x68747541
44	#define AMD_CPUID_ECX 0x444d4163	51	#define AMD_CPUID_ECX 0x444d4163
45	#define AMD_CPUID_EDX 0x69746e65	52	#define AMD_CPUID_EDX 0x69746e65
46		53
47	#define INTEL_CPUID_EBX 0x756e6547	54	#define INTEL_CPUID_EBX 0x756e6547
48	#define INTEL_CPUID_ECX 0x6c65746e	55	#define INTEL_CPUID_ECX 0x6c65746e
49	#define INTEL_CPUID_EDX 0x49656e69	56	#define INTEL_CPUID_EDX 0x49656e69
50		57
51		58
52	enum vendor {	59	enum vendor {
53	VendorUnknown=0,	60	VendorUnknown=0,
54	VendorAMD,	61	VendorAMD,
55	VendorIntel	62	VendorIntel
56	};	63	};
57		64
58	static char *vendor_str[] = {	65	static char *vendor_str[] = {
59	"Unknown Vendor",	66	"Unknown Vendor",
60	"AuthenticAMD",	67	"AuthenticAMD",
61	"GenuineIntel"	68	"GenuineIntel"
62	};	69	};
63		70
64		71
65	/** Setup flags on processor so that we can use the FPU	72	/** Setup flags on processor so that we can use the FPU
66	*	73	*
67	* cr0.osfxsr = 1 -> we do support fxstor/fxrestor	74	* cr0.osfxsr = 1 -> we do support fxstor/fxrestor
68	* cr0.em = 0 -> we do not emulate coprocessor	75	* cr0.em = 0 -> we do not emulate coprocessor
69	* cr0.mp = 1 -> we do want lazy context switch	76	* cr0.mp = 1 -> we do want lazy context switch
70	*/	77	*/
71	void cpu_setup_fpu(void)	78	void cpu_setup_fpu(void)
72	{	79	{
73	__asm__ volatile (	80	__asm__ volatile (
74	"movq %%cr0, %%rax;"	81	"movq %%cr0, %%rax;"
75	"btsq $1, %%rax;" /* cr0.mp */	82	"btsq $1, %%rax;" /* cr0.mp */
76	"btrq $2, %%rax;" /* cr0.em */	83	"btrq $2, %%rax;" /* cr0.em */
77	"movq %%rax, %%cr0;"	84	"movq %%rax, %%cr0;"
78		85
79	"movq %%cr4, %%rax;"	86	"movq %%cr4, %%rax;"
80	"bts $9, %%rax;" /* cr4.osfxsr */	87	"bts $9, %%rax;" /* cr4.osfxsr */
81	"movq %%rax, %%cr4;"	88	"movq %%rax, %%cr4;"
82	:	89	:
83	:	90	:
84	:"%rax"	91	:"%rax"
85	);	92	);
86	}	93	}
87		94
88	/** Set the TS flag to 1.	95	/** Set the TS flag to 1.
89	*	96	*
90	* If a thread accesses coprocessor, exception is run, which	97	* If a thread accesses coprocessor, exception is run, which
91	* does a lazy fpu context switch.	98	* does a lazy fpu context switch.
92	*	99	*
93	*/	100	*/
94	void fpu_disable(void)	101	void fpu_disable(void)
95	{	102	{
96	__asm__ volatile (	103	__asm__ volatile (
97	"mov %%cr0,%%rax;"	104	"mov %%cr0,%%rax;"
98	"bts $3,%%rax;"	105	"bts $3,%%rax;"
99	"mov %%rax,%%cr0;"	106	"mov %%rax,%%cr0;"
100	:	107	:
101	:	108	:
102	:"%rax"	109	:"%rax"
103	);	110	);
104	}	111	}
105		112
106	void fpu_enable(void)	113	void fpu_enable(void)
107	{	114	{
108	__asm__ volatile (	115	__asm__ volatile (
109	"mov %%cr0,%%rax;"	116	"mov %%cr0,%%rax;"
110	"btr $3,%%rax;"	117	"btr $3,%%rax;"
111	"mov %%rax,%%cr0;"	118	"mov %%rax,%%cr0;"
112	:	119	:
113	:	120	:
114	:"%rax"	121	:"%rax"
115	);	122	);
116	}	123	}
117		124
118	void cpu_arch_init(void)	125	void cpu_arch_init(void)
119	{	126	{
120	CPU->arch.tss = tss_p;	127	CPU->arch.tss = tss_p;
121	CPU->arch.tss->iomap_base = &CPU->arch.tss->iomap[0] - ((__u8 *) CPU->arch.tss);	128	CPU->arch.tss->iomap_base = &CPU->arch.tss->iomap[0] - ((__u8 *) CPU->arch.tss);
122	CPU->fpu_owner = NULL;	129	CPU->fpu_owner = NULL;
123	}	130	}
124		131
125	void cpu_identify(void)	132	void cpu_identify(void)
126	{	133	{
127	cpu_info_t info;	134	cpu_info_t info;
128		135
129	CPU->arch.vendor = VendorUnknown;	136	CPU->arch.vendor = VendorUnknown;
130	if (has_cpuid()) {	137	if (has_cpuid()) {
131	cpuid(0, &info);	138	cpuid(0, &info);
132		139
133	/*	140	/*
134	* Check for AMD processor.	141	* Check for AMD processor.
135	*/	142	*/
136	if (info.cpuid_ebx==AMD_CPUID_EBX && info.cpuid_ecx==AMD_CPUID_ECX && info.cpuid_edx==AMD_CPUID_EDX) {	143	if (info.cpuid_ebx==AMD_CPUID_EBX && info.cpuid_ecx==AMD_CPUID_ECX && info.cpuid_edx==AMD_CPUID_EDX) {
137	CPU->arch.vendor = VendorAMD;	144	CPU->arch.vendor = VendorAMD;
138	}	145	}
139		146
140	/*	147	/*
141	* Check for Intel processor.	148	* Check for Intel processor.
142	*/	149	*/
143	if (info.cpuid_ebx==INTEL_CPUID_EBX && info.cpuid_ecx==INTEL_CPUID_ECX && info.cpuid_edx==INTEL_CPUID_EDX) {	150	if (info.cpuid_ebx==INTEL_CPUID_EBX && info.cpuid_ecx==INTEL_CPUID_ECX && info.cpuid_edx==INTEL_CPUID_EDX) {
144	CPU->arch.vendor = VendorIntel;	151	CPU->arch.vendor = VendorIntel;
145	}	152	}
146		153
147	cpuid(1, &info);	154	cpuid(1, &info);
148	CPU->arch.family = (info.cpuid_eax>>8)&0xf;	155	CPU->arch.family = (info.cpuid_eax>>8)&0xf;
149	CPU->arch.model = (info.cpuid_eax>>4)&0xf;	156	CPU->arch.model = (info.cpuid_eax>>4)&0xf;
150	CPU->arch.stepping = (info.cpuid_eax>>0)&0xf;	157	CPU->arch.stepping = (info.cpuid_eax>>0)&0xf;
151	}	158	}
152	}	159	}
153		160
154	void cpu_print_report(cpu_t* m)	161	void cpu_print_report(cpu_t* m)
155	{	162	{
156	printf("cpu%d: (%s family=%d model=%d stepping=%d) %dMHz\n",	163	printf("cpu%d: (%s family=%d model=%d stepping=%d) %dMHz\n",
157	m->id, vendor_str[m->arch.vendor], m->arch.family, m->arch.model, m->arch.stepping,	164	m->id, vendor_str[m->arch.vendor], m->arch.family, m->arch.model, m->arch.stepping,
158	m->frequency_mhz);	165	m->frequency_mhz);
159	}	166	}
-		167
-		168	/** @}
-		169	*/
-		170
160		171

Subversion Repositories HelenOS-historic

(root)/kernel/trunk/arch/amd64/src/cpu/cpu.c – Rev 1187 → 1702