WebSVN – HelenOS-historic – Diff – /kernel/trunk/arch/amd64/src/amd64.c


/*
 * Copyright (C) 2005 Ondrej Palkovsky
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * - Redistributions of source code must retain the above copyright
 *   notice, this list of conditions and the following disclaimer.
 * - Redistributions in binary form must reproduce the above copyright
 *   notice, this list of conditions and the following disclaimer in the
 *   documentation and/or other materials provided with the distribution.
 * - The name of the author may not be used to endorse or promote products
 *   derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
 /** @addtogroup amd64 
 * @ingroup others
 * @{
 */
/** @file
 */
 
#include <arch.h>
 
#include <arch/types.h>
 
#include <config.h>
 
#include <proc/thread.h>
#include <arch/drivers/ega.h>
#include <arch/drivers/vesa.h>
#include <genarch/i8042/i8042.h>
#include <arch/drivers/i8254.h>
#include <arch/drivers/i8259.h>
 
#include <arch/bios/bios.h>
#include <arch/mm/memory_init.h>
#include <arch/cpu.h>
#include <print.h>
#include <arch/cpuid.h>
#include <genarch/acpi/acpi.h>
#include <panic.h>
#include <interrupt.h>
#include <arch/syscall.h>
#include <arch/debugger.h>
#include <syscall/syscall.h>
#include <console/console.h>
 
 
/** Disable I/O on non-privileged levels
 *
 * Clean IOPL(12,13) and NT(14) flags in EFLAGS register
 */
static void clean_IOPL_NT_flags(void)
{
    asm
    (
        "pushfq;"
        "pop %%rax;"
        "and $~(0x7000),%%rax;"
        "pushq %%rax;"
        "popfq;"
        :
        :
        :"%rax"
    );
}
 
/** Disable alignment check
 *
 * Clean AM(18) flag in CR0 register
 */
static void clean_AM_flag(void)
{
    asm
    (
        "mov %%cr0,%%rax;"
        "and $~(0x40000),%%rax;"
        "mov %%rax,%%cr0;"
        :
        :
        :"%rax"
    );
}
 
void arch_pre_mm_init(void)
{
    struct cpu_info cpuid_s;
 
    cpuid(AMD_CPUID_EXTENDED,&cpuid_s);
    if (! (cpuid_s.cpuid_edx & (1<<AMD_EXT_NOEXECUTE)))
        panic("Processor does not support No-execute pages.\n");
 
    cpuid(INTEL_CPUID_STANDARD,&cpuid_s);
    if (! (cpuid_s.cpuid_edx & (1<<INTEL_FXSAVE)))
        panic("Processor does not support FXSAVE/FXRESTORE.\n");
   
    if (! (cpuid_s.cpuid_edx & (1<<INTEL_SSE2)))
        panic("Processor does not support SSE2 instructions.\n");
 
    /* Enable No-execute pages */
    set_efer_flag(AMD_NXE_FLAG);
    /* Enable FPU */
    cpu_setup_fpu();
 
    /* Initialize segmentation */
    pm_init();
 
        /* Disable I/O on nonprivileged levels
     * clear the NT(nested-thread) flag
     */
    clean_IOPL_NT_flags();
    /* Disable alignment check */
    clean_AM_flag();
 
    if (config.cpu_active == 1) {
        bios_init();
        i8259_init();   /* PIC */
        i8254_init();   /* hard clock */
 
        #ifdef CONFIG_SMP
        exc_register(VECTOR_TLB_SHOOTDOWN_IPI, "tlb_shootdown",
                 tlb_shootdown_ipi);
        #endif /* CONFIG_SMP */
    }
}
 
void arch_post_mm_init(void)
{
    if (config.cpu_active == 1) {
#ifdef CONFIG_FB
        if (vesa_present())
            vesa_init();
        else
#endif
            ega_init(); /* video */
        /* Enable debugger */
        debugger_init();
        /* Merge all memory zones to 1 big zone */
        zone_merge_all();
    }
    /* Setup fast SYSCALL/SYSRET */
    syscall_setup_cpu();
   
}
 
void arch_pre_smp_init(void)
{
    if (config.cpu_active == 1) {
        memory_print_map();
       
        #ifdef CONFIG_SMP
        acpi_init();
        #endif /* CONFIG_SMP */
    }
}
 
void arch_post_smp_init(void)
{
    i8042_init();   /* keyboard controller */
}
 
void calibrate_delay_loop(void)
{
    i8254_calibrate_delay_loop();
    i8254_normal_operation();
}
 
/** Set thread-local-storage pointer
 *
 * TLS pointer is set in FS register. Unfortunately the 64-bit
 * part can be set only in CPL0 mode.
 *
 * The specs say, that on %fs:0 there is stored contents of %fs register,
 * we need not to go to CPL0 to read it.
 */
__native sys_tls_set(__native addr)
{
    THREAD->arch.tls = addr;
    write_msr(AMD_MSR_FS, addr);
    return 0;
}
 
/** Acquire console back for kernel
 *
 */
void arch_grab_console(void)
{
    i8042_grab();
}
/** Return console to userspace
 *
 */
void arch_release_console(void)
{
    i8042_release();
}
 
 /** @}
 */
 
 

Rev 1477	Rev 1702
1	/*	1	/*
2	* Copyright (C) 2005 Ondrej Palkovsky	2	* Copyright (C) 2005 Ondrej Palkovsky
3	* All rights reserved.	3	* All rights reserved.
4	*	4	*
5	* Redistribution and use in source and binary forms, with or without	5	* Redistribution and use in source and binary forms, with or without
6	* modification, are permitted provided that the following conditions	6	* modification, are permitted provided that the following conditions
7	* are met:	7	* are met:
8	*	8	*
9	* - Redistributions of source code must retain the above copyright	9	* - Redistributions of source code must retain the above copyright
10	* notice, this list of conditions and the following disclaimer.	10	* notice, this list of conditions and the following disclaimer.
11	* - Redistributions in binary form must reproduce the above copyright	11	* - Redistributions in binary form must reproduce the above copyright
12	* notice, this list of conditions and the following disclaimer in the	12	* notice, this list of conditions and the following disclaimer in the
13	* documentation and/or other materials provided with the distribution.	13	* documentation and/or other materials provided with the distribution.
14	* - The name of the author may not be used to endorse or promote products	14	* - The name of the author may not be used to endorse or promote products
15	* derived from this software without specific prior written permission.	15	* derived from this software without specific prior written permission.
16	*	16	*
17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27	*/	27	*/
28		28
-		29	/** @addtogroup amd64
-		30	* @ingroup others
-		31	* @{
-		32	*/
-		33	/** @file
-		34	*/
-		35
29	#include <arch.h>	36	#include <arch.h>
30		37
31	#include <arch/types.h>	38	#include <arch/types.h>
32		39
33	#include <config.h>	40	#include <config.h>
34		41
35	#include <proc/thread.h>	42	#include <proc/thread.h>
36	#include <arch/drivers/ega.h>	43	#include <arch/drivers/ega.h>
37	#include <arch/drivers/vesa.h>	44	#include <arch/drivers/vesa.h>
38	#include <genarch/i8042/i8042.h>	45	#include <genarch/i8042/i8042.h>
39	#include <arch/drivers/i8254.h>	46	#include <arch/drivers/i8254.h>
40	#include <arch/drivers/i8259.h>	47	#include <arch/drivers/i8259.h>
41		48
42	#include <arch/bios/bios.h>	49	#include <arch/bios/bios.h>
43	#include <arch/mm/memory_init.h>	50	#include <arch/mm/memory_init.h>
44	#include <arch/cpu.h>	51	#include <arch/cpu.h>
45	#include <print.h>	52	#include <print.h>
46	#include <arch/cpuid.h>	53	#include <arch/cpuid.h>
47	#include <genarch/acpi/acpi.h>	54	#include <genarch/acpi/acpi.h>
48	#include <panic.h>	55	#include <panic.h>
49	#include <interrupt.h>	56	#include <interrupt.h>
50	#include <arch/syscall.h>	57	#include <arch/syscall.h>
51	#include <arch/debugger.h>	58	#include <arch/debugger.h>
52	#include <syscall/syscall.h>	59	#include <syscall/syscall.h>
53	#include <console/console.h>	60	#include <console/console.h>
54		61
55		62
56	/** Disable I/O on non-privileged levels	63	/** Disable I/O on non-privileged levels
57	*	64	*
58	* Clean IOPL(12,13) and NT(14) flags in EFLAGS register	65	* Clean IOPL(12,13) and NT(14) flags in EFLAGS register
59	*/	66	*/
60	static void clean_IOPL_NT_flags(void)	67	static void clean_IOPL_NT_flags(void)
61	{	68	{
62	asm	69	asm
63	(	70	(
64	"pushfq;"	71	"pushfq;"
65	"pop %%rax;"	72	"pop %%rax;"
66	"and $~(0x7000),%%rax;"	73	"and $~(0x7000),%%rax;"
67	"pushq %%rax;"	74	"pushq %%rax;"
68	"popfq;"	75	"popfq;"
69	:	76	:
70	:	77	:
71	:"%rax"	78	:"%rax"
72	);	79	);
73	}	80	}
74		81
75	/** Disable alignment check	82	/** Disable alignment check
76	*	83	*
77	* Clean AM(18) flag in CR0 register	84	* Clean AM(18) flag in CR0 register
78	*/	85	*/
79	static void clean_AM_flag(void)	86	static void clean_AM_flag(void)
80	{	87	{
81	asm	88	asm
82	(	89	(
83	"mov %%cr0,%%rax;"	90	"mov %%cr0,%%rax;"
84	"and $~(0x40000),%%rax;"	91	"and $~(0x40000),%%rax;"
85	"mov %%rax,%%cr0;"	92	"mov %%rax,%%cr0;"
86	:	93	:
87	:	94	:
88	:"%rax"	95	:"%rax"
89	);	96	);
90	}	97	}
91		98
92	void arch_pre_mm_init(void)	99	void arch_pre_mm_init(void)
93	{	100	{
94	struct cpu_info cpuid_s;	101	struct cpu_info cpuid_s;
95		102
96	cpuid(AMD_CPUID_EXTENDED,&cpuid_s);	103	cpuid(AMD_CPUID_EXTENDED,&cpuid_s);
97	if (! (cpuid_s.cpuid_edx & (1<<AMD_EXT_NOEXECUTE)))	104	if (! (cpuid_s.cpuid_edx & (1<<AMD_EXT_NOEXECUTE)))
98	panic("Processor does not support No-execute pages.\n");	105	panic("Processor does not support No-execute pages.\n");
99		106
100	cpuid(INTEL_CPUID_STANDARD,&cpuid_s);	107	cpuid(INTEL_CPUID_STANDARD,&cpuid_s);
101	if (! (cpuid_s.cpuid_edx & (1<<INTEL_FXSAVE)))	108	if (! (cpuid_s.cpuid_edx & (1<<INTEL_FXSAVE)))
102	panic("Processor does not support FXSAVE/FXRESTORE.\n");	109	panic("Processor does not support FXSAVE/FXRESTORE.\n");
103		110
104	if (! (cpuid_s.cpuid_edx & (1<<INTEL_SSE2)))	111	if (! (cpuid_s.cpuid_edx & (1<<INTEL_SSE2)))
105	panic("Processor does not support SSE2 instructions.\n");	112	panic("Processor does not support SSE2 instructions.\n");
106		113
107	/* Enable No-execute pages */	114	/* Enable No-execute pages */
108	set_efer_flag(AMD_NXE_FLAG);	115	set_efer_flag(AMD_NXE_FLAG);
109	/* Enable FPU */	116	/* Enable FPU */
110	cpu_setup_fpu();	117	cpu_setup_fpu();
111		118
112	/* Initialize segmentation */	119	/* Initialize segmentation */
113	pm_init();	120	pm_init();
114		121
115	/* Disable I/O on nonprivileged levels	122	/* Disable I/O on nonprivileged levels
116	* clear the NT(nested-thread) flag	123	* clear the NT(nested-thread) flag
117	*/	124	*/
118	clean_IOPL_NT_flags();	125	clean_IOPL_NT_flags();
119	/* Disable alignment check */	126	/* Disable alignment check */
120	clean_AM_flag();	127	clean_AM_flag();
121		128
122	if (config.cpu_active == 1) {	129	if (config.cpu_active == 1) {
123	bios_init();	130	bios_init();
124	i8259_init(); /* PIC */	131	i8259_init(); /* PIC */
125	i8254_init(); /* hard clock */	132	i8254_init(); /* hard clock */
126		133
127	#ifdef CONFIG_SMP	134	#ifdef CONFIG_SMP
128	exc_register(VECTOR_TLB_SHOOTDOWN_IPI, "tlb_shootdown",	135	exc_register(VECTOR_TLB_SHOOTDOWN_IPI, "tlb_shootdown",
129	tlb_shootdown_ipi);	136	tlb_shootdown_ipi);
130	#endif /* CONFIG_SMP */	137	#endif /* CONFIG_SMP */
131	}	138	}
132	}	139	}
133		140
134	void arch_post_mm_init(void)	141	void arch_post_mm_init(void)
135	{	142	{
136	if (config.cpu_active == 1) {	143	if (config.cpu_active == 1) {
137	#ifdef CONFIG_FB	144	#ifdef CONFIG_FB
138	if (vesa_present())	145	if (vesa_present())
139	vesa_init();	146	vesa_init();
140	else	147	else
141	#endif	148	#endif
142	ega_init(); /* video */	149	ega_init(); /* video */
143	/* Enable debugger */	150	/* Enable debugger */
144	debugger_init();	151	debugger_init();
145	/* Merge all memory zones to 1 big zone */	152	/* Merge all memory zones to 1 big zone */
146	zone_merge_all();	153	zone_merge_all();
147	}	154	}
148	/* Setup fast SYSCALL/SYSRET */	155	/* Setup fast SYSCALL/SYSRET */
149	syscall_setup_cpu();	156	syscall_setup_cpu();
150		157
151	}	158	}
152		159
153	void arch_pre_smp_init(void)	160	void arch_pre_smp_init(void)
154	{	161	{
155	if (config.cpu_active == 1) {	162	if (config.cpu_active == 1) {
156	memory_print_map();	163	memory_print_map();
157		164
158	#ifdef CONFIG_SMP	165	#ifdef CONFIG_SMP
159	acpi_init();	166	acpi_init();
160	#endif /* CONFIG_SMP */	167	#endif /* CONFIG_SMP */
161	}	168	}
162	}	169	}
163		170
164	void arch_post_smp_init(void)	171	void arch_post_smp_init(void)
165	{	172	{
166	i8042_init(); /* keyboard controller */	173	i8042_init(); /* keyboard controller */
167	}	174	}
168		175
169	void calibrate_delay_loop(void)	176	void calibrate_delay_loop(void)
170	{	177	{
171	i8254_calibrate_delay_loop();	178	i8254_calibrate_delay_loop();
172	i8254_normal_operation();	179	i8254_normal_operation();
173	}	180	}
174		181
175	/** Set thread-local-storage pointer	182	/** Set thread-local-storage pointer
176	*	183	*
177	* TLS pointer is set in FS register. Unfortunately the 64-bit	184	* TLS pointer is set in FS register. Unfortunately the 64-bit
178	* part can be set only in CPL0 mode.	185	* part can be set only in CPL0 mode.
179	*	186	*
180	* The specs say, that on %fs:0 there is stored contents of %fs register,	187	* The specs say, that on %fs:0 there is stored contents of %fs register,
181	* we need not to go to CPL0 to read it.	188	* we need not to go to CPL0 to read it.
182	*/	189	*/
183	__native sys_tls_set(__native addr)	190	__native sys_tls_set(__native addr)
184	{	191	{
185	THREAD->arch.tls = addr;	192	THREAD->arch.tls = addr;
186	write_msr(AMD_MSR_FS, addr);	193	write_msr(AMD_MSR_FS, addr);
187	return 0;	194	return 0;
188	}	195	}
189		196
190	/** Acquire console back for kernel	197	/** Acquire console back for kernel
191	*	198	*
192	*/	199	*/
193	void arch_grab_console(void)	200	void arch_grab_console(void)
194	{	201	{
195	i8042_grab();	202	i8042_grab();
196	}	203	}
197	/** Return console to userspace	204	/** Return console to userspace
198	*	205	*
199	*/	206	*/
200	void arch_release_console(void)	207	void arch_release_console(void)
201	{	208	{
202	i8042_release();	209	i8042_release();
203	}	210	}
-		211
-		212	/** @}
-		213	*/
-		214
204		215

Subversion Repositories HelenOS-historic

(root)/kernel/trunk/arch/amd64/src/amd64.c – Rev 1477 → 1702