WebSVN – HelenOS-historic – Diff – /kernel/trunk/arch/amd64/include/asm.h


/*
 * Copyright (C) 2005 Jakub Jermar
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * - Redistributions of source code must retain the above copyright
 *   notice, this list of conditions and the following disclaimer.
 * - Redistributions in binary form must reproduce the above copyright
 *   notice, this list of conditions and the following disclaimer in the
 *   documentation and/or other materials provided with the distribution.
 * - The name of the author may not be used to endorse or promote products
 *   derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
 /** @addtogroup amd64 
 * @{
 */
/** @file
 */
 
#ifndef __amd64_ASM_H__
#define __amd64_ASM_H__
 
#include <arch/pm.h>
#include <arch/types.h>
#include <config.h>
 
extern void asm_delay_loop(uint32_t t);
extern void asm_fake_loop(uint32_t t);
 
/** Return base address of current stack.
 *
 * Return the base address of the current stack.
 * The stack is assumed to be STACK_SIZE bytes long.
 * The stack must start on page boundary.
 */
static inline uintptr_t get_stack_base(void)
{
    uintptr_t v;
   
    __asm__ volatile ("andq %%rsp, %0\n" : "=r" (v) : "0" (~((uint64_t)STACK_SIZE-1)));
   
    return v;
}
 
static inline void cpu_sleep(void) { __asm__ volatile ("hlt\n"); };
static inline void cpu_halt(void) { __asm__ volatile ("hlt\n"); };
 
 
/** Byte from port
 *
 * Get byte from port
 *
 * @param port Port to read from
 * @return Value read
 */
static inline uint8_t inb(uint16_t port) { uint8_t val; __asm__ volatile ("inb %w1, %b0 \n" : "=a" (val) : "d" (port) ); return val; }
 
/** Byte to port
 *
 * Output byte to port
 *
 * @param port Port to write to
 * @param val Value to write
 */
static inline void outb(uint16_t port, uint8_t val) { __asm__ volatile ("outb %b0, %w1\n" : : "a" (val), "d" (port) ); }
 
/** Swap Hidden part of GS register with visible one */
static inline void swapgs(void) { __asm__ volatile("swapgs"); }
 
/** Enable interrupts.
 *
 * Enable interrupts and return previous
 * value of EFLAGS.
 *
 * @return Old interrupt priority level.
 */
static inline ipl_t interrupts_enable(void) {
    ipl_t v;
    __asm__ volatile (
        "pushfq\n"
        "popq %0\n"
        "sti\n"
        : "=r" (v)
    );
    return v;
}
 
/** Disable interrupts.
 *
 * Disable interrupts and return previous
 * value of EFLAGS.
 *
 * @return Old interrupt priority level.
 */
static inline ipl_t interrupts_disable(void) {
    ipl_t v;
    __asm__ volatile (
        "pushfq\n"
        "popq %0\n"
        "cli\n"
        : "=r" (v)
        );
    return v;
}
 
/** Restore interrupt priority level.
 *
 * Restore EFLAGS.
 *
 * @param ipl Saved interrupt priority level.
 */
static inline void interrupts_restore(ipl_t ipl) {
    __asm__ volatile (
        "pushq %0\n"
        "popfq\n"
        : : "r" (ipl)
        );
}
 
/** Return interrupt priority level.
 *
 * Return EFLAFS.
 *
 * @return Current interrupt priority level.
 */
static inline ipl_t interrupts_read(void) {
    ipl_t v;
    __asm__ volatile (
        "pushfq\n"
        "popq %0\n"
        : "=r" (v)
    );
    return v;
}
 
/** Write to MSR */
static inline void write_msr(uint32_t msr, uint64_t value)
{
    __asm__ volatile (
        "wrmsr;" : : "c" (msr),
        "a" ((uint32_t)(value)),
        "d" ((uint32_t)(value >> 32))
        );
}
 
static inline unative_t read_msr(uint32_t msr)
{
    uint32_t ax, dx;
 
    __asm__ volatile (
        "rdmsr;" : "=a"(ax), "=d"(dx) : "c" (msr)
        );
    return ((uint64_t)dx << 32) | ax;
}
 
 
/** Enable local APIC
 *
 * Enable local APIC in MSR.
 */
static inline void enable_l_apic_in_msr()
{
    __asm__ volatile (
        "movl $0x1b, %%ecx\n"
        "rdmsr\n"
        "orl $(1<<11),%%eax\n"
        "orl $(0xfee00000),%%eax\n"
        "wrmsr\n"
        :
        :
        :"%eax","%ecx","%edx"
        );
}
 
static inline uintptr_t * get_ip()
{
    uintptr_t *ip;
 
    __asm__ volatile (
        "mov %%rip, %0"
        : "=r" (ip)
        );
    return ip;
}
 
/** Invalidate TLB Entry.
 *
 * @param addr Address on a page whose TLB entry is to be invalidated.
 */
static inline void invlpg(uintptr_t addr)
{
    __asm__ volatile ("invlpg %0\n" :: "m" (*((unative_t *)addr)));
}
 
/** Load GDTR register from memory.
 *
 * @param gdtr_reg Address of memory from where to load GDTR.
 */
static inline void gdtr_load(struct ptr_16_64 *gdtr_reg)
{
    __asm__ volatile ("lgdtq %0\n" : : "m" (*gdtr_reg));
}
 
/** Store GDTR register to memory.
 *
 * @param gdtr_reg Address of memory to where to load GDTR.
 */
static inline void gdtr_store(struct ptr_16_64 *gdtr_reg)
{
    __asm__ volatile ("sgdtq %0\n" : : "m" (*gdtr_reg));
}
 
/** Load IDTR register from memory.
 *
 * @param idtr_reg Address of memory from where to load IDTR.
 */
static inline void idtr_load(struct ptr_16_64 *idtr_reg)
{
    __asm__ volatile ("lidtq %0\n" : : "m" (*idtr_reg));
}
 
/** Load TR from descriptor table.
 *
 * @param sel Selector specifying descriptor of TSS segment.
 */
static inline void tr_load(uint16_t sel)
{
    __asm__ volatile ("ltr %0" : : "r" (sel));
}
 
#define GEN_READ_REG(reg) static inline unative_t read_ ##reg (void) \
    { \
    unative_t res; \
    __asm__ volatile ("movq %%" #reg ", %0" : "=r" (res) ); \
    return res; \
    }
 
#define GEN_WRITE_REG(reg) static inline void write_ ##reg (unative_t regn) \
    { \
    __asm__ volatile ("movq %0, %%" #reg : : "r" (regn)); \
    }
 
GEN_READ_REG(cr0);
GEN_READ_REG(cr2);
GEN_READ_REG(cr3);
GEN_WRITE_REG(cr3);
 
GEN_READ_REG(dr0);
GEN_READ_REG(dr1);
GEN_READ_REG(dr2);
GEN_READ_REG(dr3);
GEN_READ_REG(dr6);
GEN_READ_REG(dr7);
 
GEN_WRITE_REG(dr0);
GEN_WRITE_REG(dr1);
GEN_WRITE_REG(dr2);
GEN_WRITE_REG(dr3);
GEN_WRITE_REG(dr6);
GEN_WRITE_REG(dr7);
 
 
extern size_t interrupt_handler_size;
extern void interrupt_handlers(void);
 
#endif
 
 /** @}
 */
 
 

Rev 1702	Rev 1780
1	/*	1	/*
2	* Copyright (C) 2005 Jakub Jermar	2	* Copyright (C) 2005 Jakub Jermar
3	* All rights reserved.	3	* All rights reserved.
4	*	4	*
5	* Redistribution and use in source and binary forms, with or without	5	* Redistribution and use in source and binary forms, with or without
6	* modification, are permitted provided that the following conditions	6	* modification, are permitted provided that the following conditions
7	* are met:	7	* are met:
8	*	8	*
9	* - Redistributions of source code must retain the above copyright	9	* - Redistributions of source code must retain the above copyright
10	* notice, this list of conditions and the following disclaimer.	10	* notice, this list of conditions and the following disclaimer.
11	* - Redistributions in binary form must reproduce the above copyright	11	* - Redistributions in binary form must reproduce the above copyright
12	* notice, this list of conditions and the following disclaimer in the	12	* notice, this list of conditions and the following disclaimer in the
13	* documentation and/or other materials provided with the distribution.	13	* documentation and/or other materials provided with the distribution.
14	* - The name of the author may not be used to endorse or promote products	14	* - The name of the author may not be used to endorse or promote products
15	* derived from this software without specific prior written permission.	15	* derived from this software without specific prior written permission.
16	*	16	*
17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27	*/	27	*/
28		28
29	/** @addtogroup amd64	29	/** @addtogroup amd64
30	* @{	30	* @{
31	*/	31	*/
32	/** @file	32	/** @file
33	*/	33	*/
34		34
35	#ifndef __amd64_ASM_H__	35	#ifndef __amd64_ASM_H__
36	#define __amd64_ASM_H__	36	#define __amd64_ASM_H__
37		37
38	#include <arch/pm.h>	38	#include <arch/pm.h>
39	#include <arch/types.h>	39	#include <arch/types.h>
40	#include <config.h>	40	#include <config.h>
41		41
42	extern void asm_delay_loop(__u32 t);	42	extern void asm_delay_loop(uint32_t t);
43	extern void asm_fake_loop(__u32 t);	43	extern void asm_fake_loop(uint32_t t);
44		44
45	/** Return base address of current stack.	45	/** Return base address of current stack.
46	*	46	*
47	* Return the base address of the current stack.	47	* Return the base address of the current stack.
48	* The stack is assumed to be STACK_SIZE bytes long.	48	* The stack is assumed to be STACK_SIZE bytes long.
49	* The stack must start on page boundary.	49	* The stack must start on page boundary.
50	*/	50	*/
51	static inline __address get_stack_base(void)	51	static inline uintptr_t get_stack_base(void)
52	{	52	{
53	__address v;	53	uintptr_t v;
54		54
55	__asm__ volatile ("andq %%rsp, %0\n" : "=r" (v) : "0" (~((__u64)STACK_SIZE-1)));	55	__asm__ volatile ("andq %%rsp, %0\n" : "=r" (v) : "0" (~((uint64_t)STACK_SIZE-1)));
56		56
57	return v;	57	return v;
58	}	58	}
59		59
60	static inline void cpu_sleep(void) { __asm__ volatile ("hlt\n"); };	60	static inline void cpu_sleep(void) { __asm__ volatile ("hlt\n"); };
61	static inline void cpu_halt(void) { __asm__ volatile ("hlt\n"); };	61	static inline void cpu_halt(void) { __asm__ volatile ("hlt\n"); };
62		62
63		63
64	/** Byte from port	64	/** Byte from port
65	*	65	*
66	* Get byte from port	66	* Get byte from port
67	*	67	*
68	* @param port Port to read from	68	* @param port Port to read from
69	* @return Value read	69	* @return Value read
70	*/	70	*/
71	static inline __u8 inb(__u16 port) { __u8 val; __asm__ volatile ("inb %w1, %b0 \n" : "=a" (val) : "d" (port) ); return val; }	71	static inline uint8_t inb(uint16_t port) { uint8_t val; __asm__ volatile ("inb %w1, %b0 \n" : "=a" (val) : "d" (port) ); return val; }
72		72
73	/** Byte to port	73	/** Byte to port
74	*	74	*
75	* Output byte to port	75	* Output byte to port
76	*	76	*
77	* @param port Port to write to	77	* @param port Port to write to
78	* @param val Value to write	78	* @param val Value to write
79	*/	79	*/
80	static inline void outb(__u16 port, __u8 val) { __asm__ volatile ("outb %b0, %w1\n" : : "a" (val), "d" (port) ); }	80	static inline void outb(uint16_t port, uint8_t val) { __asm__ volatile ("outb %b0, %w1\n" : : "a" (val), "d" (port) ); }
81		81
82	/** Swap Hidden part of GS register with visible one */	82	/** Swap Hidden part of GS register with visible one */
83	static inline void swapgs(void) { __asm__ volatile("swapgs"); }	83	static inline void swapgs(void) { __asm__ volatile("swapgs"); }
84		84
85	/** Enable interrupts.	85	/** Enable interrupts.
86	*	86	*
87	* Enable interrupts and return previous	87	* Enable interrupts and return previous
88	* value of EFLAGS.	88	* value of EFLAGS.
89	*	89	*
90	* @return Old interrupt priority level.	90	* @return Old interrupt priority level.
91	*/	91	*/
92	static inline ipl_t interrupts_enable(void) {	92	static inline ipl_t interrupts_enable(void) {
93	ipl_t v;	93	ipl_t v;
94	__asm__ volatile (	94	__asm__ volatile (
95	"pushfq\n"	95	"pushfq\n"
96	"popq %0\n"	96	"popq %0\n"
97	"sti\n"	97	"sti\n"
98	: "=r" (v)	98	: "=r" (v)
99	);	99	);
100	return v;	100	return v;
101	}	101	}
102		102
103	/** Disable interrupts.	103	/** Disable interrupts.
104	*	104	*
105	* Disable interrupts and return previous	105	* Disable interrupts and return previous
106	* value of EFLAGS.	106	* value of EFLAGS.
107	*	107	*
108	* @return Old interrupt priority level.	108	* @return Old interrupt priority level.
109	*/	109	*/
110	static inline ipl_t interrupts_disable(void) {	110	static inline ipl_t interrupts_disable(void) {
111	ipl_t v;	111	ipl_t v;
112	__asm__ volatile (	112	__asm__ volatile (
113	"pushfq\n"	113	"pushfq\n"
114	"popq %0\n"	114	"popq %0\n"
115	"cli\n"	115	"cli\n"
116	: "=r" (v)	116	: "=r" (v)
117	);	117	);
118	return v;	118	return v;
119	}	119	}
120		120
121	/** Restore interrupt priority level.	121	/** Restore interrupt priority level.
122	*	122	*
123	* Restore EFLAGS.	123	* Restore EFLAGS.
124	*	124	*
125	* @param ipl Saved interrupt priority level.	125	* @param ipl Saved interrupt priority level.
126	*/	126	*/
127	static inline void interrupts_restore(ipl_t ipl) {	127	static inline void interrupts_restore(ipl_t ipl) {
128	__asm__ volatile (	128	__asm__ volatile (
129	"pushq %0\n"	129	"pushq %0\n"
130	"popfq\n"	130	"popfq\n"
131	: : "r" (ipl)	131	: : "r" (ipl)
132	);	132	);
133	}	133	}
134		134
135	/** Return interrupt priority level.	135	/** Return interrupt priority level.
136	*	136	*
137	* Return EFLAFS.	137	* Return EFLAFS.
138	*	138	*
139	* @return Current interrupt priority level.	139	* @return Current interrupt priority level.
140	*/	140	*/
141	static inline ipl_t interrupts_read(void) {	141	static inline ipl_t interrupts_read(void) {
142	ipl_t v;	142	ipl_t v;
143	__asm__ volatile (	143	__asm__ volatile (
144	"pushfq\n"	144	"pushfq\n"
145	"popq %0\n"	145	"popq %0\n"
146	: "=r" (v)	146	: "=r" (v)
147	);	147	);
148	return v;	148	return v;
149	}	149	}
150		150
151	/** Write to MSR */	151	/** Write to MSR */
152	static inline void write_msr(__u32 msr, __u64 value)	152	static inline void write_msr(uint32_t msr, uint64_t value)
153	{	153	{
154	__asm__ volatile (	154	__asm__ volatile (
155	"wrmsr;" : : "c" (msr),	155	"wrmsr;" : : "c" (msr),
156	"a" ((__u32)(value)),	156	"a" ((uint32_t)(value)),
157	"d" ((__u32)(value >> 32))	157	"d" ((uint32_t)(value >> 32))
158	);	158	);
159	}	159	}
160		160
161	static inline __native read_msr(__u32 msr)	161	static inline unative_t read_msr(uint32_t msr)
162	{	162	{
163	__u32 ax, dx;	163	uint32_t ax, dx;
164		164
165	__asm__ volatile (	165	__asm__ volatile (
166	"rdmsr;" : "=a"(ax), "=d"(dx) : "c" (msr)	166	"rdmsr;" : "=a"(ax), "=d"(dx) : "c" (msr)
167	);	167	);
168	return ((__u64)dx << 32) \| ax;	168	return ((uint64_t)dx << 32) \| ax;
169	}	169	}
170		170
171		171
172	/** Enable local APIC	172	/** Enable local APIC
173	*	173	*
174	* Enable local APIC in MSR.	174	* Enable local APIC in MSR.
175	*/	175	*/
176	static inline void enable_l_apic_in_msr()	176	static inline void enable_l_apic_in_msr()
177	{	177	{
178	__asm__ volatile (	178	__asm__ volatile (
179	"movl $0x1b, %%ecx\n"	179	"movl $0x1b, %%ecx\n"
180	"rdmsr\n"	180	"rdmsr\n"
181	"orl $(1<<11),%%eax\n"	181	"orl $(1<<11),%%eax\n"
182	"orl $(0xfee00000),%%eax\n"	182	"orl $(0xfee00000),%%eax\n"
183	"wrmsr\n"	183	"wrmsr\n"
184	:	184	:
185	:	185	:
186	:"%eax","%ecx","%edx"	186	:"%eax","%ecx","%edx"
187	);	187	);
188	}	188	}
189		189
190	static inline __address * get_ip()	190	static inline uintptr_t * get_ip()
191	{	191	{
192	__address *ip;	192	uintptr_t *ip;
193		193
194	__asm__ volatile (	194	__asm__ volatile (
195	"mov %%rip, %0"	195	"mov %%rip, %0"
196	: "=r" (ip)	196	: "=r" (ip)
197	);	197	);
198	return ip;	198	return ip;
199	}	199	}
200		200
201	/** Invalidate TLB Entry.	201	/** Invalidate TLB Entry.
202	*	202	*
203	* @param addr Address on a page whose TLB entry is to be invalidated.	203	* @param addr Address on a page whose TLB entry is to be invalidated.
204	*/	204	*/
205	static inline void invlpg(__address addr)	205	static inline void invlpg(uintptr_t addr)
206	{	206	{
207	__asm__ volatile ("invlpg %0\n" :: "m" (((__native )addr)));	207	__asm__ volatile ("invlpg %0\n" :: "m" (((unative_t )addr)));
208	}	208	}
209		209
210	/** Load GDTR register from memory.	210	/** Load GDTR register from memory.
211	*	211	*
212	* @param gdtr_reg Address of memory from where to load GDTR.	212	* @param gdtr_reg Address of memory from where to load GDTR.
213	*/	213	*/
214	static inline void gdtr_load(struct ptr_16_64 *gdtr_reg)	214	static inline void gdtr_load(struct ptr_16_64 *gdtr_reg)
215	{	215	{
216	__asm__ volatile ("lgdtq %0\n" : : "m" (*gdtr_reg));	216	__asm__ volatile ("lgdtq %0\n" : : "m" (*gdtr_reg));
217	}	217	}
218		218
219	/** Store GDTR register to memory.	219	/** Store GDTR register to memory.
220	*	220	*
221	* @param gdtr_reg Address of memory to where to load GDTR.	221	* @param gdtr_reg Address of memory to where to load GDTR.
222	*/	222	*/
223	static inline void gdtr_store(struct ptr_16_64 *gdtr_reg)	223	static inline void gdtr_store(struct ptr_16_64 *gdtr_reg)
224	{	224	{
225	__asm__ volatile ("sgdtq %0\n" : : "m" (*gdtr_reg));	225	__asm__ volatile ("sgdtq %0\n" : : "m" (*gdtr_reg));
226	}	226	}
227		227
228	/** Load IDTR register from memory.	228	/** Load IDTR register from memory.
229	*	229	*
230	* @param idtr_reg Address of memory from where to load IDTR.	230	* @param idtr_reg Address of memory from where to load IDTR.
231	*/	231	*/
232	static inline void idtr_load(struct ptr_16_64 *idtr_reg)	232	static inline void idtr_load(struct ptr_16_64 *idtr_reg)
233	{	233	{
234	__asm__ volatile ("lidtq %0\n" : : "m" (*idtr_reg));	234	__asm__ volatile ("lidtq %0\n" : : "m" (*idtr_reg));
235	}	235	}
236		236
237	/** Load TR from descriptor table.	237	/** Load TR from descriptor table.
238	*	238	*
239	* @param sel Selector specifying descriptor of TSS segment.	239	* @param sel Selector specifying descriptor of TSS segment.
240	*/	240	*/
241	static inline void tr_load(__u16 sel)	241	static inline void tr_load(uint16_t sel)
242	{	242	{
243	__asm__ volatile ("ltr %0" : : "r" (sel));	243	__asm__ volatile ("ltr %0" : : "r" (sel));
244	}	244	}
245		245
246	#define GEN_READ_REG(reg) static inline __native read_ ##reg (void) \	246	#define GEN_READ_REG(reg) static inline unative_t read_ ##reg (void) \
247	{ \	247	{ \
248	__native res; \	248	unative_t res; \
249	__asm__ volatile ("movq %%" #reg ", %0" : "=r" (res) ); \	249	__asm__ volatile ("movq %%" #reg ", %0" : "=r" (res) ); \
250	return res; \	250	return res; \
251	}	251	}
252		252
253	#define GEN_WRITE_REG(reg) static inline void write_ ##reg (__native regn) \	253	#define GEN_WRITE_REG(reg) static inline void write_ ##reg (unative_t regn) \
254	{ \	254	{ \
255	__asm__ volatile ("movq %0, %%" #reg : : "r" (regn)); \	255	__asm__ volatile ("movq %0, %%" #reg : : "r" (regn)); \
256	}	256	}
257		257
258	GEN_READ_REG(cr0);	258	GEN_READ_REG(cr0);
259	GEN_READ_REG(cr2);	259	GEN_READ_REG(cr2);
260	GEN_READ_REG(cr3);	260	GEN_READ_REG(cr3);
261	GEN_WRITE_REG(cr3);	261	GEN_WRITE_REG(cr3);
262		262
263	GEN_READ_REG(dr0);	263	GEN_READ_REG(dr0);
264	GEN_READ_REG(dr1);	264	GEN_READ_REG(dr1);
265	GEN_READ_REG(dr2);	265	GEN_READ_REG(dr2);
266	GEN_READ_REG(dr3);	266	GEN_READ_REG(dr3);
267	GEN_READ_REG(dr6);	267	GEN_READ_REG(dr6);
268	GEN_READ_REG(dr7);	268	GEN_READ_REG(dr7);
269		269
270	GEN_WRITE_REG(dr0);	270	GEN_WRITE_REG(dr0);
271	GEN_WRITE_REG(dr1);	271	GEN_WRITE_REG(dr1);
272	GEN_WRITE_REG(dr2);	272	GEN_WRITE_REG(dr2);
273	GEN_WRITE_REG(dr3);	273	GEN_WRITE_REG(dr3);
274	GEN_WRITE_REG(dr6);	274	GEN_WRITE_REG(dr6);
275	GEN_WRITE_REG(dr7);	275	GEN_WRITE_REG(dr7);
276		276
277		277
278	extern size_t interrupt_handler_size;	278	extern size_t interrupt_handler_size;
279	extern void interrupt_handlers(void);	279	extern void interrupt_handlers(void);
280		280
281	#endif	281	#endif
282		282
283	/** @}	283	/** @}
284	*/	284	*/
285		285
286		286

Subversion Repositories HelenOS-historic

(root)/kernel/trunk/arch/amd64/include/asm.h – Rev 1702 → 1780