WebSVN – HelenOS-historic – Diff – /kernel/trunk/arch/amd64/include/asm.h


/*
 * Copyright (C) 2005 Jakub Jermar
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * - Redistributions of source code must retain the above copyright
 *   notice, this list of conditions and the following disclaimer.
 * - Redistributions in binary form must reproduce the above copyright
 *   notice, this list of conditions and the following disclaimer in the
 *   documentation and/or other materials provided with the distribution.
 * - The name of the author may not be used to endorse or promote products
 *   derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
 /** @addtogroup amd64 
 * @{
 */
/** @file
 */
 
#ifndef __amd64_ASM_H__
#define __amd64_ASM_H__
 
#include <arch/pm.h>
#include <arch/types.h>
#include <config.h>
 
extern void asm_delay_loop(__u32 t);
extern void asm_fake_loop(__u32 t);
 
/** Return base address of current stack.
 *
 * Return the base address of the current stack.
 * The stack is assumed to be STACK_SIZE bytes long.
 * The stack must start on page boundary.
 */
static inline __address get_stack_base(void)
{
    __address v;
   
    __asm__ volatile ("andq %%rsp, %0\n" : "=r" (v) : "0" (~((__u64)STACK_SIZE-1)));
   
    return v;
}
 
static inline void cpu_sleep(void) { __asm__ volatile ("hlt\n"); };
static inline void cpu_halt(void) { __asm__ volatile ("hlt\n"); };
 
 
/** Byte from port
 *
 * Get byte from port
 *
 * @param port Port to read from
 * @return Value read
 */
static inline __u8 inb(__u16 port) { __u8 val; __asm__ volatile ("inb %w1, %b0 \n" : "=a" (val) : "d" (port) ); return val; }
 
/** Byte to port
 *
 * Output byte to port
 *
 * @param port Port to write to
 * @param val Value to write
 */
static inline void outb(__u16 port, __u8 val) { __asm__ volatile ("outb %b0, %w1\n" : : "a" (val), "d" (port) ); }
 
/** Swap Hidden part of GS register with visible one */
static inline void swapgs(void) { __asm__ volatile("swapgs"); }
 
/** Enable interrupts.
 *
 * Enable interrupts and return previous
 * value of EFLAGS.
 *
 * @return Old interrupt priority level.
 */
static inline ipl_t interrupts_enable(void) {
    ipl_t v;
    __asm__ volatile (
        "pushfq\n"
        "popq %0\n"
        "sti\n"
        : "=r" (v)
    );
    return v;
}
 
/** Disable interrupts.
 *
 * Disable interrupts and return previous
 * value of EFLAGS.
 *
 * @return Old interrupt priority level.
 */
static inline ipl_t interrupts_disable(void) {
    ipl_t v;
    __asm__ volatile (
        "pushfq\n"
        "popq %0\n"
        "cli\n"
        : "=r" (v)
        );
    return v;
}
 
/** Restore interrupt priority level.
 *
 * Restore EFLAGS.
 *
 * @param ipl Saved interrupt priority level.
 */
static inline void interrupts_restore(ipl_t ipl) {
    __asm__ volatile (
        "pushq %0\n"
        "popfq\n"
        : : "r" (ipl)
        );
}
 
/** Return interrupt priority level.
 *
 * Return EFLAFS.
 *
 * @return Current interrupt priority level.
 */
static inline ipl_t interrupts_read(void) {
    ipl_t v;
    __asm__ volatile (
        "pushfq\n"
        "popq %0\n"
        : "=r" (v)
    );
    return v;
}
 
/** Write to MSR */
static inline void write_msr(__u32 msr, __u64 value)
{
    __asm__ volatile (
        "wrmsr;" : : "c" (msr),
        "a" ((__u32)(value)),
        "d" ((__u32)(value >> 32))
        );
}
 
static inline __native read_msr(__u32 msr)
{
    __u32 ax, dx;
 
    __asm__ volatile (
        "rdmsr;" : "=a"(ax), "=d"(dx) : "c" (msr)
        );
    return ((__u64)dx << 32) | ax;
}
 
 
/** Enable local APIC
 *
 * Enable local APIC in MSR.
 */
static inline void enable_l_apic_in_msr()
{
    __asm__ volatile (
        "movl $0x1b, %%ecx\n"
        "rdmsr\n"
        "orl $(1<<11),%%eax\n"
        "orl $(0xfee00000),%%eax\n"
        "wrmsr\n"
        :
        :
        :"%eax","%ecx","%edx"
        );
}
 
static inline __address * get_ip()
{
    __address *ip;
 
    __asm__ volatile (
        "mov %%rip, %0"
        : "=r" (ip)
        );
    return ip;
}
 
/** Invalidate TLB Entry.
 *
 * @param addr Address on a page whose TLB entry is to be invalidated.
 */
static inline void invlpg(__address addr)
{
    __asm__ volatile ("invlpg %0\n" :: "m" (*((__native *)addr)));
}
 
/** Load GDTR register from memory.
 *
 * @param gdtr_reg Address of memory from where to load GDTR.
 */
static inline void gdtr_load(struct ptr_16_64 *gdtr_reg)
{
    __asm__ volatile ("lgdtq %0\n" : : "m" (*gdtr_reg));
}
 
/** Store GDTR register to memory.
 *
 * @param gdtr_reg Address of memory to where to load GDTR.
 */
static inline void gdtr_store(struct ptr_16_64 *gdtr_reg)
{
    __asm__ volatile ("sgdtq %0\n" : : "m" (*gdtr_reg));
}
 
/** Load IDTR register from memory.
 *
 * @param idtr_reg Address of memory from where to load IDTR.
 */
static inline void idtr_load(struct ptr_16_64 *idtr_reg)
{
    __asm__ volatile ("lidtq %0\n" : : "m" (*idtr_reg));
}
 
/** Load TR from descriptor table.
 *
 * @param sel Selector specifying descriptor of TSS segment.
 */
static inline void tr_load(__u16 sel)
{
    __asm__ volatile ("ltr %0" : : "r" (sel));
}
 
#define GEN_READ_REG(reg) static inline __native read_ ##reg (void) \
    { \
    __native res; \
    __asm__ volatile ("movq %%" #reg ", %0" : "=r" (res) ); \
    return res; \
    }
 
#define GEN_WRITE_REG(reg) static inline void write_ ##reg (__native regn) \
    { \
    __asm__ volatile ("movq %0, %%" #reg : : "r" (regn)); \
    }
 
GEN_READ_REG(cr0);
GEN_READ_REG(cr2);
GEN_READ_REG(cr3);
GEN_WRITE_REG(cr3);
 
GEN_READ_REG(dr0);
GEN_READ_REG(dr1);
GEN_READ_REG(dr2);
GEN_READ_REG(dr3);
GEN_READ_REG(dr6);
GEN_READ_REG(dr7);
 
GEN_WRITE_REG(dr0);
GEN_WRITE_REG(dr1);
GEN_WRITE_REG(dr2);
GEN_WRITE_REG(dr3);
GEN_WRITE_REG(dr6);
GEN_WRITE_REG(dr7);
 
 
extern size_t interrupt_handler_size;
extern void interrupt_handlers(void);
 
#endif
 
 /** @}
 */
 
 

Rev 1251	Rev 1702
1	/*	1	/*
2	* Copyright (C) 2005 Jakub Jermar	2	* Copyright (C) 2005 Jakub Jermar
3	* All rights reserved.	3	* All rights reserved.
4	*	4	*
5	* Redistribution and use in source and binary forms, with or without	5	* Redistribution and use in source and binary forms, with or without
6	* modification, are permitted provided that the following conditions	6	* modification, are permitted provided that the following conditions
7	* are met:	7	* are met:
8	*	8	*
9	* - Redistributions of source code must retain the above copyright	9	* - Redistributions of source code must retain the above copyright
10	* notice, this list of conditions and the following disclaimer.	10	* notice, this list of conditions and the following disclaimer.
11	* - Redistributions in binary form must reproduce the above copyright	11	* - Redistributions in binary form must reproduce the above copyright
12	* notice, this list of conditions and the following disclaimer in the	12	* notice, this list of conditions and the following disclaimer in the
13	* documentation and/or other materials provided with the distribution.	13	* documentation and/or other materials provided with the distribution.
14	* - The name of the author may not be used to endorse or promote products	14	* - The name of the author may not be used to endorse or promote products
15	* derived from this software without specific prior written permission.	15	* derived from this software without specific prior written permission.
16	*	16	*
17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27	*/	27	*/
28		28
-		29	/** @addtogroup amd64
-		30	* @{
-		31	*/
-		32	/** @file
-		33	*/
-		34
29	#ifndef __amd64_ASM_H__	35	#ifndef __amd64_ASM_H__
30	#define __amd64_ASM_H__	36	#define __amd64_ASM_H__
31		37
32	#include <arch/pm.h>	38	#include <arch/pm.h>
33	#include <arch/types.h>	39	#include <arch/types.h>
34	#include <config.h>	40	#include <config.h>
35		41
36	extern void asm_delay_loop(__u32 t);	42	extern void asm_delay_loop(__u32 t);
37	extern void asm_fake_loop(__u32 t);	43	extern void asm_fake_loop(__u32 t);
38		44
39	/** Return base address of current stack.	45	/** Return base address of current stack.
40	*	46	*
41	* Return the base address of the current stack.	47	* Return the base address of the current stack.
42	* The stack is assumed to be STACK_SIZE bytes long.	48	* The stack is assumed to be STACK_SIZE bytes long.
43	* The stack must start on page boundary.	49	* The stack must start on page boundary.
44	*/	50	*/
45	static inline __address get_stack_base(void)	51	static inline __address get_stack_base(void)
46	{	52	{
47	__address v;	53	__address v;
48		54
49	__asm__ volatile ("andq %%rsp, %0\n" : "=r" (v) : "0" (~((__u64)STACK_SIZE-1)));	55	__asm__ volatile ("andq %%rsp, %0\n" : "=r" (v) : "0" (~((__u64)STACK_SIZE-1)));
50		56
51	return v;	57	return v;
52	}	58	}
53		59
54	static inline void cpu_sleep(void) { __asm__ volatile ("hlt\n"); };	60	static inline void cpu_sleep(void) { __asm__ volatile ("hlt\n"); };
55	static inline void cpu_halt(void) { __asm__ volatile ("hlt\n"); };	61	static inline void cpu_halt(void) { __asm__ volatile ("hlt\n"); };
56		62
57		63
58	/** Byte from port	64	/** Byte from port
59	*	65	*
60	* Get byte from port	66	* Get byte from port
61	*	67	*
62	* @param port Port to read from	68	* @param port Port to read from
63	* @return Value read	69	* @return Value read
64	*/	70	*/
65	static inline __u8 inb(__u16 port) { __u8 val; __asm__ volatile ("inb %w1, %b0 \n" : "=a" (val) : "d" (port) ); return val; }	71	static inline __u8 inb(__u16 port) { __u8 val; __asm__ volatile ("inb %w1, %b0 \n" : "=a" (val) : "d" (port) ); return val; }
66		72
67	/** Byte to port	73	/** Byte to port
68	*	74	*
69	* Output byte to port	75	* Output byte to port
70	*	76	*
71	* @param port Port to write to	77	* @param port Port to write to
72	* @param val Value to write	78	* @param val Value to write
73	*/	79	*/
74	static inline void outb(__u16 port, __u8 val) { __asm__ volatile ("outb %b0, %w1\n" : : "a" (val), "d" (port) ); }	80	static inline void outb(__u16 port, __u8 val) { __asm__ volatile ("outb %b0, %w1\n" : : "a" (val), "d" (port) ); }
75		81
76	/** Swap Hidden part of GS register with visible one */	82	/** Swap Hidden part of GS register with visible one */
77	static inline void swapgs(void) { __asm__ volatile("swapgs"); }	83	static inline void swapgs(void) { __asm__ volatile("swapgs"); }
78		84
79	/** Enable interrupts.	85	/** Enable interrupts.
80	*	86	*
81	* Enable interrupts and return previous	87	* Enable interrupts and return previous
82	* value of EFLAGS.	88	* value of EFLAGS.
83	*	89	*
84	* @return Old interrupt priority level.	90	* @return Old interrupt priority level.
85	*/	91	*/
86	static inline ipl_t interrupts_enable(void) {	92	static inline ipl_t interrupts_enable(void) {
87	ipl_t v;	93	ipl_t v;
88	__asm__ volatile (	94	__asm__ volatile (
89	"pushfq\n"	95	"pushfq\n"
90	"popq %0\n"	96	"popq %0\n"
91	"sti\n"	97	"sti\n"
92	: "=r" (v)	98	: "=r" (v)
93	);	99	);
94	return v;	100	return v;
95	}	101	}
96		102
97	/** Disable interrupts.	103	/** Disable interrupts.
98	*	104	*
99	* Disable interrupts and return previous	105	* Disable interrupts and return previous
100	* value of EFLAGS.	106	* value of EFLAGS.
101	*	107	*
102	* @return Old interrupt priority level.	108	* @return Old interrupt priority level.
103	*/	109	*/
104	static inline ipl_t interrupts_disable(void) {	110	static inline ipl_t interrupts_disable(void) {
105	ipl_t v;	111	ipl_t v;
106	__asm__ volatile (	112	__asm__ volatile (
107	"pushfq\n"	113	"pushfq\n"
108	"popq %0\n"	114	"popq %0\n"
109	"cli\n"	115	"cli\n"
110	: "=r" (v)	116	: "=r" (v)
111	);	117	);
112	return v;	118	return v;
113	}	119	}
114		120
115	/** Restore interrupt priority level.	121	/** Restore interrupt priority level.
116	*	122	*
117	* Restore EFLAGS.	123	* Restore EFLAGS.
118	*	124	*
119	* @param ipl Saved interrupt priority level.	125	* @param ipl Saved interrupt priority level.
120	*/	126	*/
121	static inline void interrupts_restore(ipl_t ipl) {	127	static inline void interrupts_restore(ipl_t ipl) {
122	__asm__ volatile (	128	__asm__ volatile (
123	"pushq %0\n"	129	"pushq %0\n"
124	"popfq\n"	130	"popfq\n"
125	: : "r" (ipl)	131	: : "r" (ipl)
126	);	132	);
127	}	133	}
128		134
129	/** Return interrupt priority level.	135	/** Return interrupt priority level.
130	*	136	*
131	* Return EFLAFS.	137	* Return EFLAFS.
132	*	138	*
133	* @return Current interrupt priority level.	139	* @return Current interrupt priority level.
134	*/	140	*/
135	static inline ipl_t interrupts_read(void) {	141	static inline ipl_t interrupts_read(void) {
136	ipl_t v;	142	ipl_t v;
137	__asm__ volatile (	143	__asm__ volatile (
138	"pushfq\n"	144	"pushfq\n"
139	"popq %0\n"	145	"popq %0\n"
140	: "=r" (v)	146	: "=r" (v)
141	);	147	);
142	return v;	148	return v;
143	}	149	}
144		150
145	/** Write to MSR */	151	/** Write to MSR */
146	static inline void write_msr(__u32 msr, __u64 value)	152	static inline void write_msr(__u32 msr, __u64 value)
147	{	153	{
148	__asm__ volatile (	154	__asm__ volatile (
149	"wrmsr;" : : "c" (msr),	155	"wrmsr;" : : "c" (msr),
150	"a" ((__u32)(value)),	156	"a" ((__u32)(value)),
151	"d" ((__u32)(value >> 32))	157	"d" ((__u32)(value >> 32))
152	);	158	);
153	}	159	}
154		160
155	static inline __native read_msr(__u32 msr)	161	static inline __native read_msr(__u32 msr)
156	{	162	{
157	__u32 ax, dx;	163	__u32 ax, dx;
158		164
159	__asm__ volatile (	165	__asm__ volatile (
160	"rdmsr;" : "=a"(ax), "=d"(dx) : "c" (msr)	166	"rdmsr;" : "=a"(ax), "=d"(dx) : "c" (msr)
161	);	167	);
162	return ((__u64)dx << 32) \| ax;	168	return ((__u64)dx << 32) \| ax;
163	}	169	}
164		170
165		171
166	/** Enable local APIC	172	/** Enable local APIC
167	*	173	*
168	* Enable local APIC in MSR.	174	* Enable local APIC in MSR.
169	*/	175	*/
170	static inline void enable_l_apic_in_msr()	176	static inline void enable_l_apic_in_msr()
171	{	177	{
172	__asm__ volatile (	178	__asm__ volatile (
173	"movl $0x1b, %%ecx\n"	179	"movl $0x1b, %%ecx\n"
174	"rdmsr\n"	180	"rdmsr\n"
175	"orl $(1<<11),%%eax\n"	181	"orl $(1<<11),%%eax\n"
176	"orl $(0xfee00000),%%eax\n"	182	"orl $(0xfee00000),%%eax\n"
177	"wrmsr\n"	183	"wrmsr\n"
178	:	184	:
179	:	185	:
180	:"%eax","%ecx","%edx"	186	:"%eax","%ecx","%edx"
181	);	187	);
182	}	188	}
183		189
184	static inline __address * get_ip()	190	static inline __address * get_ip()
185	{	191	{
186	__address *ip;	192	__address *ip;
187		193
188	__asm__ volatile (	194	__asm__ volatile (
189	"mov %%rip, %0"	195	"mov %%rip, %0"
190	: "=r" (ip)	196	: "=r" (ip)
191	);	197	);
192	return ip;	198	return ip;
193	}	199	}
194		200
195	/** Invalidate TLB Entry.	201	/** Invalidate TLB Entry.
196	*	202	*
197	* @param addr Address on a page whose TLB entry is to be invalidated.	203	* @param addr Address on a page whose TLB entry is to be invalidated.
198	*/	204	*/
199	static inline void invlpg(__address addr)	205	static inline void invlpg(__address addr)
200	{	206	{
201	__asm__ volatile ("invlpg %0\n" :: "m" (((__native )addr)));	207	__asm__ volatile ("invlpg %0\n" :: "m" (((__native )addr)));
202	}	208	}
203		209
204	/** Load GDTR register from memory.	210	/** Load GDTR register from memory.
205	*	211	*
206	* @param gdtr_reg Address of memory from where to load GDTR.	212	* @param gdtr_reg Address of memory from where to load GDTR.
207	*/	213	*/
208	static inline void gdtr_load(struct ptr_16_64 *gdtr_reg)	214	static inline void gdtr_load(struct ptr_16_64 *gdtr_reg)
209	{	215	{
210	__asm__ volatile ("lgdtq %0\n" : : "m" (*gdtr_reg));	216	__asm__ volatile ("lgdtq %0\n" : : "m" (*gdtr_reg));
211	}	217	}
212		218
213	/** Store GDTR register to memory.	219	/** Store GDTR register to memory.
214	*	220	*
215	* @param gdtr_reg Address of memory to where to load GDTR.	221	* @param gdtr_reg Address of memory to where to load GDTR.
216	*/	222	*/
217	static inline void gdtr_store(struct ptr_16_64 *gdtr_reg)	223	static inline void gdtr_store(struct ptr_16_64 *gdtr_reg)
218	{	224	{
219	__asm__ volatile ("sgdtq %0\n" : : "m" (*gdtr_reg));	225	__asm__ volatile ("sgdtq %0\n" : : "m" (*gdtr_reg));
220	}	226	}
221		227
222	/** Load IDTR register from memory.	228	/** Load IDTR register from memory.
223	*	229	*
224	* @param idtr_reg Address of memory from where to load IDTR.	230	* @param idtr_reg Address of memory from where to load IDTR.
225	*/	231	*/
226	static inline void idtr_load(struct ptr_16_64 *idtr_reg)	232	static inline void idtr_load(struct ptr_16_64 *idtr_reg)
227	{	233	{
228	__asm__ volatile ("lidtq %0\n" : : "m" (*idtr_reg));	234	__asm__ volatile ("lidtq %0\n" : : "m" (*idtr_reg));
229	}	235	}
230		236
231	/** Load TR from descriptor table.	237	/** Load TR from descriptor table.
232	*	238	*
233	* @param sel Selector specifying descriptor of TSS segment.	239	* @param sel Selector specifying descriptor of TSS segment.
234	*/	240	*/
235	static inline void tr_load(__u16 sel)	241	static inline void tr_load(__u16 sel)
236	{	242	{
237	__asm__ volatile ("ltr %0" : : "r" (sel));	243	__asm__ volatile ("ltr %0" : : "r" (sel));
238	}	244	}
239		245
240	#define GEN_READ_REG(reg) static inline __native read_ ##reg (void) \	246	#define GEN_READ_REG(reg) static inline __native read_ ##reg (void) \
241	{ \	247	{ \
242	__native res; \	248	__native res; \
243	__asm__ volatile ("movq %%" #reg ", %0" : "=r" (res) ); \	249	__asm__ volatile ("movq %%" #reg ", %0" : "=r" (res) ); \
244	return res; \	250	return res; \
245	}	251	}
246		252
247	#define GEN_WRITE_REG(reg) static inline void write_ ##reg (__native regn) \	253	#define GEN_WRITE_REG(reg) static inline void write_ ##reg (__native regn) \
248	{ \	254	{ \
249	__asm__ volatile ("movq %0, %%" #reg : : "r" (regn)); \	255	__asm__ volatile ("movq %0, %%" #reg : : "r" (regn)); \
250	}	256	}
251		257
252	GEN_READ_REG(cr0);	258	GEN_READ_REG(cr0);
253	GEN_READ_REG(cr2);	259	GEN_READ_REG(cr2);
254	GEN_READ_REG(cr3);	260	GEN_READ_REG(cr3);
255	GEN_WRITE_REG(cr3);	261	GEN_WRITE_REG(cr3);
256		262
257	GEN_READ_REG(dr0);	263	GEN_READ_REG(dr0);
258	GEN_READ_REG(dr1);	264	GEN_READ_REG(dr1);
259	GEN_READ_REG(dr2);	265	GEN_READ_REG(dr2);
260	GEN_READ_REG(dr3);	266	GEN_READ_REG(dr3);
261	GEN_READ_REG(dr6);	267	GEN_READ_REG(dr6);
262	GEN_READ_REG(dr7);	268	GEN_READ_REG(dr7);
263		269
264	GEN_WRITE_REG(dr0);	270	GEN_WRITE_REG(dr0);
265	GEN_WRITE_REG(dr1);	271	GEN_WRITE_REG(dr1);
266	GEN_WRITE_REG(dr2);	272	GEN_WRITE_REG(dr2);
267	GEN_WRITE_REG(dr3);	273	GEN_WRITE_REG(dr3);
268	GEN_WRITE_REG(dr6);	274	GEN_WRITE_REG(dr6);
269	GEN_WRITE_REG(dr7);	275	GEN_WRITE_REG(dr7);
270		276
271		277
272	extern size_t interrupt_handler_size;	278	extern size_t interrupt_handler_size;
273	extern void interrupt_handlers(void);	279	extern void interrupt_handlers(void);
274		280
275	#endif	281	#endif
-		282
-		283	/** @}
-		284	*/
-		285
276		286

Subversion Repositories HelenOS-historic

(root)/kernel/trunk/arch/amd64/include/asm.h – Rev 1251 → 1702