WebSVN – HelenOS-historic – Diff – /boot/trunk/arch/ppc32/loader/asm.S


#
# Copyright (C) 2006 Martin Decky
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions
# are met:
#
# - Redistributions of source code must retain the above copyright
#   notice, this list of conditions and the following disclaimer.
# - Redistributions in binary form must reproduce the above copyright
#   notice, this list of conditions and the following disclaimer in the
#   documentation and/or other materials provided with the distribution.
# - The name of the author may not be used to endorse or promote products
#   derived from this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
 
#include "regname.h"
#include "spr.h"
 
.data
 
flush_buffer:
	.space (L1_CACHE_LINES * L1_CACHE_BYTES)
 
.text
 
.global memsetb
.global memcpy
.global flush_instruction_cache
.global jump_to_kernel
 
memsetb:
	rlwimi r5, r5, 8, 16, 23
	rlwimi r5, r5, 16, 0, 15
	
	addi r14, r3, -4
	
	cmplwi 0, r4, 4
	blt 7f
	
	stwu r5, 4(r14)
	beqlr
	
	andi. r15, r14, 3
	add r4, r15, r4
	subf r14, r15, r14
	srwi r15, r4, 2
	mtctr r15
	
	bdz 6f
	
	1:
		stwu r5, 4(r14)
		bdnz 1b
	
	6:
	
	andi. r4, r4, 3
	
	7:
	
	cmpwi 0, r4, 0
	beqlr
	
	mtctr r4
	addi r6, r6, 3
	
	8:
	
	stbu r5, 1(r14)
	bdnz 8b
	
	blr
 
memcpy:
	srwi. r7, r5, 3
	addi r6, r3, -4
	addi r4, r4, -4
	beq	2f
	
	andi. r0, r6, 3
	mtctr r7
	bne 5f
	
	1:
	
	lwz r7, 4(r4)
	lwzu r8, 8(r4)
	stw r7, 4(r6)
	stwu r8, 8(r6)
	bdnz 1b
	
	andi. r5, r5, 7
	
	2:
	
	cmplwi 0, r5, 4
	blt 3f
	
	lwzu r0, 4(r4)
	addi r5, r5, -4
	stwu r0, 4(r6)
	
	3:
	
	cmpwi 0, r5, 0
	beqlr
	mtctr r5
	addi r4, r4, 3
	addi r6, r6, 3
	
	4:
	
	lbzu r0, 1(r4)
	stbu r0, 1(r6)
	bdnz 4b
	blr
	
	5:
	
	subfic r0, r0, 4
	mtctr r0
	
	6:
	
	lbz r7, 4(r4)
	addi r4, r4, 1
	stb r7, 4(r6)
	addi r6, r6, 1
	bdnz 6b
	subf r5, r0, r5
	rlwinm. r7, r5, 32-3, 3, 31
	beq 2b
	mtctr r7
	b 1b
	
flush_instruction_cache:
 
	# Flush data cache
	
	lis r3, flush_buffer@h
	ori r3, r3, flush_buffer@l
	li r4, L1_CACHE_LINES
	mtctr r4
	
	0:
	
	lwz r4, 0(r3)
	addi r3, r3, L1_CACHE_BYTES
	bdnz 0b
	
	# Invalidate instruction cache
	
	li r3, 0
	ori	r3, r3, (HID0_ICE | HID0_DCE | HID0_ICFI | HID0_DCI)
	mfspr r4, SPRN_HID0
	or r5, r4, r3
	isync
	mtspr SPRN_HID0, r5
	sync
	isync
	
	# Enable instruction cache
	
	ori	r5, r4, HID0_ICE
	mtspr SPRN_HID0, r5
	sync
	isync
	blr
 
jump_to_kernel:
 
	mtlr r3
	blr
 
 
 
 
 
 

Rev 953	Rev 956
1	#	1	#
2	# Copyright (C) 2006 Martin Decky	2	# Copyright (C) 2006 Martin Decky
3	# All rights reserved.	3	# All rights reserved.
4	#	4	#
5	# Redistribution and use in source and binary forms, with or without	5	# Redistribution and use in source and binary forms, with or without
6	# modification, are permitted provided that the following conditions	6	# modification, are permitted provided that the following conditions
7	# are met:	7	# are met:
8	#	8	#
9	# - Redistributions of source code must retain the above copyright	9	# - Redistributions of source code must retain the above copyright
10	# notice, this list of conditions and the following disclaimer.	10	# notice, this list of conditions and the following disclaimer.
11	# - Redistributions in binary form must reproduce the above copyright	11	# - Redistributions in binary form must reproduce the above copyright
12	# notice, this list of conditions and the following disclaimer in the	12	# notice, this list of conditions and the following disclaimer in the
13	# documentation and/or other materials provided with the distribution.	13	# documentation and/or other materials provided with the distribution.
14	# - The name of the author may not be used to endorse or promote products	14	# - The name of the author may not be used to endorse or promote products
15	# derived from this software without specific prior written permission.	15	# derived from this software without specific prior written permission.
16	#	16	#
17	# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	17	# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18	# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	18	# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19	# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	19	# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20	# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	20	# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21	# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	21	# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22	# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	22	# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23	# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	23	# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24	# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	24	# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25	# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	25	# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26	# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	26	# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27	#	27	#
28		28
29	#include "regname.h"	29	#include "regname.h"
30	#include "spr.h"	30	#include "spr.h"
31		31
32	.data	32	.data
33		33
34	flush_buffer:	34	flush_buffer:
35	.space (L1_CACHE_LINES * L1_CACHE_BYTES)	35	.space (L1_CACHE_LINES * L1_CACHE_BYTES)
36		36
37	.text	37	.text
38		38
39	.global memsetb	39	.global memsetb
40	.global memcpy	40	.global memcpy
-		41	.global flush_instruction_cache
41	.global jump_to_kernel	42	.global jump_to_kernel
42		43
43	memsetb:	44	memsetb:
44	rlwimi r5, r5, 8, 16, 23	45	rlwimi r5, r5, 8, 16, 23
45	rlwimi r5, r5, 16, 0, 15	46	rlwimi r5, r5, 16, 0, 15
46		47
47	addi r14, r3, -4	48	addi r14, r3, -4
48		49
49	cmplwi 0, r4, 4	50	cmplwi 0, r4, 4
50	blt 7f	51	blt 7f
51		52
52	stwu r5, 4(r14)	53	stwu r5, 4(r14)
53	beqlr	54	beqlr
54		55
55	andi. r15, r14, 3	56	andi. r15, r14, 3
56	add r4, r15, r4	57	add r4, r15, r4
57	subf r14, r15, r14	58	subf r14, r15, r14
58	srwi r15, r4, 2	59	srwi r15, r4, 2
59	mtctr r15	60	mtctr r15
60		61
61	bdz 6f	62	bdz 6f
62		63
63	1:	64	1:
64	stwu r5, 4(r14)	65	stwu r5, 4(r14)
65	bdnz 1b	66	bdnz 1b
66		67
67	6:	68	6:
68		69
69	andi. r4, r4, 3	70	andi. r4, r4, 3
70		71
71	7:	72	7:
72		73
73	cmpwi 0, r4, 0	74	cmpwi 0, r4, 0
74	beqlr	75	beqlr
75		76
76	mtctr r4	77	mtctr r4
77	addi r6, r6, 3	78	addi r6, r6, 3
78		79
79	8:	80	8:
80		81
81	stbu r5, 1(r14)	82	stbu r5, 1(r14)
82	bdnz 8b	83	bdnz 8b
83		84
84	blr	85	blr
85		86
86	memcpy:	87	memcpy:
87	srwi. r7, r5, 3	88	srwi. r7, r5, 3
88	addi r6, r3, -4	89	addi r6, r3, -4
89	addi r4, r4, -4	90	addi r4, r4, -4
90	beq 2f	91	beq 2f
91		92
92	andi. r0, r6, 3	93	andi. r0, r6, 3
93	mtctr r7	94	mtctr r7
94	bne 5f	95	bne 5f
95		96
96	1:	97	1:
97		98
98	lwz r7, 4(r4)	99	lwz r7, 4(r4)
99	lwzu r8, 8(r4)	100	lwzu r8, 8(r4)
100	stw r7, 4(r6)	101	stw r7, 4(r6)
101	stwu r8, 8(r6)	102	stwu r8, 8(r6)
102	bdnz 1b	103	bdnz 1b
103		104
104	andi. r5, r5, 7	105	andi. r5, r5, 7
105		106
106	2:	107	2:
107		108
108	cmplwi 0, r5, 4	109	cmplwi 0, r5, 4
109	blt 3f	110	blt 3f
110		111
111	lwzu r0, 4(r4)	112	lwzu r0, 4(r4)
112	addi r5, r5, -4	113	addi r5, r5, -4
113	stwu r0, 4(r6)	114	stwu r0, 4(r6)
114		115
115	3:	116	3:
116		117
117	cmpwi 0, r5, 0	118	cmpwi 0, r5, 0
118	beqlr	119	beqlr
119	mtctr r5	120	mtctr r5
120	addi r4, r4, 3	121	addi r4, r4, 3
121	addi r6, r6, 3	122	addi r6, r6, 3
122		123
123	4:	124	4:
124		125
125	lbzu r0, 1(r4)	126	lbzu r0, 1(r4)
126	stbu r0, 1(r6)	127	stbu r0, 1(r6)
127	bdnz 4b	128	bdnz 4b
128	blr	129	blr
129		130
130	5:	131	5:
131		132
132	subfic r0, r0, 4	133	subfic r0, r0, 4
133	mtctr r0	134	mtctr r0
134		135
135	6:	136	6:
136		137
137	lbz r7, 4(r4)	138	lbz r7, 4(r4)
138	addi r4, r4, 1	139	addi r4, r4, 1
139	stb r7, 4(r6)	140	stb r7, 4(r6)
140	addi r6, r6, 1	141	addi r6, r6, 1
141	bdnz 6b	142	bdnz 6b
142	subf r5, r0, r5	143	subf r5, r0, r5
143	rlwinm. r7, r5, 32-3, 3, 31	144	rlwinm. r7, r5, 32-3, 3, 31
144	beq 2b	145	beq 2b
145	mtctr r7	146	mtctr r7
146	b 1b	147	b 1b
147		148
148	flush_instruction_cache:	149	flush_instruction_cache:
149		150
150	# Flush data cache	151	# Flush data cache
151		152
152	lis r3, flush_buffer@h	153	lis r3, flush_buffer@h
153	ori r3, r3, flush_buffer@l	154	ori r3, r3, flush_buffer@l
154	li r4, L1_CACHE_LINES	155	li r4, L1_CACHE_LINES
155	mtctr r4	156	mtctr r4
156		157
157	0:	158	0:
158		159
159	lwz r4, 0(r3)	160	lwz r4, 0(r3)
160	addi r3, r3, L1_CACHE_BYTES	161	addi r3, r3, L1_CACHE_BYTES
161	bdnz 0b	162	bdnz 0b
162		163
163	# Invalidate instruction cache	164	# Invalidate instruction cache
164		165
165	li r3, 0	166	li r3, 0
166	ori r3, r3, (HID0_ICE \| HID0_DCE \| HID0_ICFI \| HID0_DCI)	167	ori r3, r3, (HID0_ICE \| HID0_DCE \| HID0_ICFI \| HID0_DCI)
167	mfspr r4, SPRN_HID0	168	mfspr r4, SPRN_HID0
168	or r5, r4, r3	169	or r5, r4, r3
169	isync	170	isync
170	mtspr SPRN_HID0, r5	171	mtspr SPRN_HID0, r5
171	sync	172	sync
172	isync	173	isync
173		174
174	# Enable instruction cache	175	# Enable instruction cache
175		176
176	ori r5, r4, HID0_ICE	177	ori r5, r4, HID0_ICE
177	mtspr SPRN_HID0, r5	178	mtspr SPRN_HID0, r5
178	sync	179	sync
179	isync	180	isync
180	blr	181	blr
181		182
182	jump_to_kernel:	183	jump_to_kernel:
183	mtspr SPRN_SRR0, r3	-
184	mfmsr r3	184	mtlr r3
185	lis r4, ~0@h	185	blr
186	ori r4, r4, ~(MSR_IR \| MSR_DR)@l	-
187	and r3, r3, r4	-
188	mtspr SPRN_SRR1, r3	-
189	bl flush_instruction_cache	-
190	rfi	186
191		187

Subversion Repositories HelenOS-historic

(root)/boot/trunk/arch/ppc32/loader/asm.S – Rev 953 → 956