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| 1 | # |
1 | # |
| 2 | # Copyright (C) 2006 Martin Decky |
2 | # Copyright (C) 2006 Martin Decky |
| 3 | # All rights reserved. |
3 | # All rights reserved. |
| 4 | # |
4 | # |
| 5 | # Redistribution and use in source and binary forms, with or without |
5 | # Redistribution and use in source and binary forms, with or without |
| 6 | # modification, are permitted provided that the following conditions |
6 | # modification, are permitted provided that the following conditions |
| 7 | # are met: |
7 | # are met: |
| 8 | # |
8 | # |
| 9 | # - Redistributions of source code must retain the above copyright |
9 | # - Redistributions of source code must retain the above copyright |
| 10 | # notice, this list of conditions and the following disclaimer. |
10 | # notice, this list of conditions and the following disclaimer. |
| 11 | # - Redistributions in binary form must reproduce the above copyright |
11 | # - Redistributions in binary form must reproduce the above copyright |
| 12 | # notice, this list of conditions and the following disclaimer in the |
12 | # notice, this list of conditions and the following disclaimer in the |
| 13 | # documentation and/or other materials provided with the distribution. |
13 | # documentation and/or other materials provided with the distribution. |
| 14 | # - The name of the author may not be used to endorse or promote products |
14 | # - The name of the author may not be used to endorse or promote products |
| 15 | # derived from this software without specific prior written permission. |
15 | # derived from this software without specific prior written permission. |
| 16 | # |
16 | # |
| 17 | # THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
17 | # THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
| 18 | # IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
18 | # IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
| 19 | # OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
19 | # OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
| 20 | # IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
20 | # IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
| 21 | # INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
21 | # INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
| 22 | # NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
22 | # NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
| 23 | # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
23 | # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
| 24 | # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
24 | # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 25 | # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
25 | # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
| 26 | # THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
26 | # THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 27 | # |
27 | # |
| 28 | 28 | ||
| 29 | #include "regname.h" |
29 | #include "regname.h" |
| 30 | #include "spr.h" |
30 | #include "spr.h" |
| 31 | 31 | ||
| - | 32 | .data |
|
| - | 33 | ||
| - | 34 | flush_buffer: |
|
| - | 35 | .space 4 |
|
| - | 36 | ||
| 32 | .text |
37 | .text |
| 33 | 38 | ||
| 34 | .global memsetb |
39 | .global memsetb |
| 35 | .global memcpy |
40 | .global memcpy |
| 36 | .global halt |
41 | .global halt |
| 37 | .global jump_to_kernel |
42 | .global jump_to_kernel |
| 38 | 43 | ||
| 39 | memsetb: |
44 | memsetb: |
| 40 | rlwimi r5, r5, 8, 16, 23 |
45 | rlwimi r5, r5, 8, 16, 23 |
| 41 | rlwimi r5, r5, 16, 0, 15 |
46 | rlwimi r5, r5, 16, 0, 15 |
| 42 | 47 | ||
| 43 | addi r14, r3, -4 |
48 | addi r14, r3, -4 |
| 44 | 49 | ||
| 45 | cmplwi 0, r4, 4 |
50 | cmplwi 0, r4, 4 |
| 46 | blt 7f |
51 | blt 7f |
| 47 | 52 | ||
| 48 | stwu r5, 4(r14) |
53 | stwu r5, 4(r14) |
| 49 | beqlr |
54 | beqlr |
| 50 | 55 | ||
| 51 | andi. r15, r14, 3 |
56 | andi. r15, r14, 3 |
| 52 | add r4, r15, r4 |
57 | add r4, r15, r4 |
| 53 | subf r14, r15, r14 |
58 | subf r14, r15, r14 |
| 54 | srwi r15, r4, 2 |
59 | srwi r15, r4, 2 |
| 55 | mtctr r15 |
60 | mtctr r15 |
| 56 | 61 | ||
| 57 | bdz 6f |
62 | bdz 6f |
| 58 | 63 | ||
| 59 | 1: |
64 | 1: |
| 60 | stwu r5, 4(r14) |
65 | stwu r5, 4(r14) |
| 61 | bdnz 1b |
66 | bdnz 1b |
| 62 | 67 | ||
| 63 | 6: |
68 | 6: |
| 64 | 69 | ||
| 65 | andi. r4, r4, 3 |
70 | andi. r4, r4, 3 |
| 66 | 71 | ||
| 67 | 7: |
72 | 7: |
| 68 | 73 | ||
| 69 | cmpwi 0, r4, 0 |
74 | cmpwi 0, r4, 0 |
| 70 | beqlr |
75 | beqlr |
| 71 | 76 | ||
| 72 | mtctr r4 |
77 | mtctr r4 |
| 73 | addi r6, r6, 3 |
78 | addi r6, r6, 3 |
| 74 | 79 | ||
| 75 | 8: |
80 | 8: |
| 76 | 81 | ||
| 77 | stbu r5, 1(r14) |
82 | stbu r5, 1(r14) |
| 78 | bdnz 8b |
83 | bdnz 8b |
| 79 | 84 | ||
| 80 | blr |
85 | blr |
| 81 | 86 | ||
| 82 | memcpy: |
87 | memcpy: |
| 83 | srwi. r7, r5, 3 |
88 | srwi. r7, r5, 3 |
| 84 | addi r6, r3, -4 |
89 | addi r6, r3, -4 |
| 85 | addi r4, r4, -4 |
90 | addi r4, r4, -4 |
| 86 | beq 2f |
91 | beq 2f |
| 87 | 92 | ||
| 88 | andi. r0, r6, 3 |
93 | andi. r0, r6, 3 |
| 89 | mtctr r7 |
94 | mtctr r7 |
| 90 | bne 5f |
95 | bne 5f |
| 91 | 96 | ||
| 92 | 1: |
97 | 1: |
| 93 | 98 | ||
| 94 | lwz r7, 4(r4) |
99 | lwz r7, 4(r4) |
| 95 | lwzu r8, 8(r4) |
100 | lwzu r8, 8(r4) |
| 96 | stw r7, 4(r6) |
101 | stw r7, 4(r6) |
| 97 | stwu r8, 8(r6) |
102 | stwu r8, 8(r6) |
| 98 | bdnz 1b |
103 | bdnz 1b |
| 99 | 104 | ||
| 100 | andi. r5, r5, 7 |
105 | andi. r5, r5, 7 |
| 101 | 106 | ||
| 102 | 2: |
107 | 2: |
| 103 | 108 | ||
| 104 | cmplwi 0, r5, 4 |
109 | cmplwi 0, r5, 4 |
| 105 | blt 3f |
110 | blt 3f |
| 106 | 111 | ||
| 107 | lwzu r0, 4(r4) |
112 | lwzu r0, 4(r4) |
| 108 | addi r5, r5, -4 |
113 | addi r5, r5, -4 |
| 109 | stwu r0, 4(r6) |
114 | stwu r0, 4(r6) |
| 110 | 115 | ||
| 111 | 3: |
116 | 3: |
| 112 | 117 | ||
| 113 | cmpwi 0, r5, 0 |
118 | cmpwi 0, r5, 0 |
| 114 | beqlr |
119 | beqlr |
| 115 | mtctr r5 |
120 | mtctr r5 |
| 116 | addi r4, r4, 3 |
121 | addi r4, r4, 3 |
| 117 | addi r6, r6, 3 |
122 | addi r6, r6, 3 |
| 118 | 123 | ||
| 119 | 4: |
124 | 4: |
| 120 | 125 | ||
| 121 | lbzu r0, 1(r4) |
126 | lbzu r0, 1(r4) |
| 122 | stbu r0, 1(r6) |
127 | stbu r0, 1(r6) |
| 123 | bdnz 4b |
128 | bdnz 4b |
| 124 | blr |
129 | blr |
| 125 | 130 | ||
| 126 | 5: |
131 | 5: |
| 127 | 132 | ||
| 128 | subfic r0, r0, 4 |
133 | subfic r0, r0, 4 |
| 129 | mtctr r0 |
134 | mtctr r0 |
| 130 | 135 | ||
| 131 | 6: |
136 | 6: |
| 132 | 137 | ||
| 133 | lbz r7, 4(r4) |
138 | lbz r7, 4(r4) |
| 134 | addi r4, r4, 1 |
139 | addi r4, r4, 1 |
| 135 | stb r7, 4(r6) |
140 | stb r7, 4(r6) |
| 136 | addi r6, r6, 1 |
141 | addi r6, r6, 1 |
| 137 | bdnz 6b |
142 | bdnz 6b |
| 138 | subf r5, r0, r5 |
143 | subf r5, r0, r5 |
| 139 | rlwinm. r7, r5, 32-3, 3, 31 |
144 | rlwinm. r7, r5, 32-3, 3, 31 |
| 140 | beq 2b |
145 | beq 2b |
| 141 | mtctr r7 |
146 | mtctr r7 |
| 142 | b 1b |
147 | b 1b |
| 143 | 148 | ||
| 144 | halt: |
149 | halt: |
| 145 | b halt |
150 | b halt |
| 146 | 151 | ||
| - | 152 | flush_instruction_cache: |
|
| - | 153 | ||
| - | 154 | # Flush data cache |
|
| - | 155 | ||
| - | 156 | lis r3, flush_buffer@h |
|
| - | 157 | ori r3, r3, flush_buffer@l |
|
| - | 158 | li r4, L1_CACHE_LINES |
|
| - | 159 | mtctr r4 |
|
| - | 160 | ||
| - | 161 | 0: |
|
| - | 162 | ||
| - | 163 | lwz r4, 0(r3) |
|
| - | 164 | addi r3, r3, L1_CACHE_BYTES |
|
| - | 165 | bdnz 0b |
|
| - | 166 | ||
| - | 167 | # Invalidate instruction cache |
|
| - | 168 | ||
| - | 169 | li r3, 0 |
|
| - | 170 | ori r3, r3, (HID0_ICE | HID0_DCE | HID0_ICFI | HID0_DCI) |
|
| - | 171 | mfspr r4, SPRN_HID0 |
|
| - | 172 | or r5, r4, r3 |
|
| - | 173 | isync |
|
| - | 174 | mtspr SPRN_HID0, r5 |
|
| - | 175 | sync |
|
| - | 176 | isync |
|
| - | 177 | ||
| - | 178 | # Enable instruction cache |
|
| - | 179 | ||
| - | 180 | ori r5, r4, HID0_ICE |
|
| - | 181 | mtspr SPRN_HID0, r5 |
|
| - | 182 | sync |
|
| - | 183 | isync |
|
| - | 184 | blr |
|
| - | 185 | ||
| 147 | jump_to_kernel: |
186 | jump_to_kernel: |
| 148 | mfmsr r4 |
187 | mfmsr r4 |
| 149 | andis. r4, r4, (~MSR_DR | MSR_IR) >> 16 |
188 | andis. r4, r4, (~MSR_DR | MSR_IR) >> 16 |
| 150 | mtspr SPRN_SRR0, r3 |
189 | mtspr SPRN_SRR0, r3 |
| 151 | mtspr SPRN_SRR1, r4 |
190 | mtspr SPRN_SRR1, r4 |
| 152 | sync |
191 | bl flush_instruction_cache |
| 153 | RFI |
192 | rfi |
| 154 | 193 | ||