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#
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#
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# Copyright (C) 2006 Martin Decky
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# Copyright (C) 2006 Martin Decky
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# All rights reserved.
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# All rights reserved.
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#
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#
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# Redistribution and use in source and binary forms, with or without
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions
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# modification, are permitted provided that the following conditions
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# are met:
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# are met:
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#
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#
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# - Redistributions of source code must retain the above copyright
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# - Redistributions of source code must retain the above copyright
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#   notice, this list of conditions and the following disclaimer.
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#   notice, this list of conditions and the following disclaimer.
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# - Redistributions in binary form must reproduce the above copyright
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# - Redistributions in binary form must reproduce the above copyright
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#   notice, this list of conditions and the following disclaimer in the
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#   notice, this list of conditions and the following disclaimer in the
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#   documentation and/or other materials provided with the distribution.
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#   documentation and/or other materials provided with the distribution.
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# - The name of the author may not be used to endorse or promote products
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# - The name of the author may not be used to endorse or promote products
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#   derived from this software without specific prior written permission.
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#   derived from this software without specific prior written permission.
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#
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#
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# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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#
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#include "asm.h"
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#include "asm.h"
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#include "regname.h"
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#include "regname.h"
-
 
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#include "debug.inc"
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.text
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.text
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.global halt
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.global halt
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.global memcpy
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.global memcpy
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.global jump_to_kernel
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.global jump_to_kernel
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halt:
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halt:
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	b halt
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	b halt
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memcpy:
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memcpy:
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	srwi. r7, r5, 3
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	srwi. r7, r5, 3
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	addi r6, r3, -4
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	addi r6, r3, -4
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	addi r4, r4, -4
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	addi r4, r4, -4
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	beq	2f
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	beq	2f
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47
	
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	andi. r0, r6, 3
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	andi. r0, r6, 3
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	mtctr r7
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	mtctr r7
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	bne 5f
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	bne 5f
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51
	
51
	1:
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	1:
52
	
53
	
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	lwz r7, 4(r4)
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	lwz r7, 4(r4)
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	lwzu r8, 8(r4)
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	lwzu r8, 8(r4)
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	stw r7, 4(r6)
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	stw r7, 4(r6)
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	stwu r8, 8(r6)
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	stwu r8, 8(r6)
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	bdnz 1b
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	bdnz 1b
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59
	
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	andi. r5, r5, 7
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	andi. r5, r5, 7
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61
	
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	2:
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	2:
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63
	
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	cmplwi 0, r5, 4
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	cmplwi 0, r5, 4
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	blt 3f
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	blt 3f
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66
	
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	lwzu r0, 4(r4)
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	lwzu r0, 4(r4)
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	addi r5, r5, -4
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	addi r5, r5, -4
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	stwu r0, 4(r6)
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	stwu r0, 4(r6)
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	3:
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	3:
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	cmpwi 0, r5, 0
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	cmpwi 0, r5, 0
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	beqlr
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	beqlr
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	mtctr r5
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	mtctr r5
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	addi r4, r4, 3
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	addi r4, r4, 3
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	addi r6, r6, 3
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	addi r6, r6, 3
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	4:
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	4:
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	lbzu r0, 1(r4)
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	lbzu r0, 1(r4)
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	stbu r0, 1(r6)
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	stbu r0, 1(r6)
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	bdnz 4b
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	bdnz 4b
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	blr
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	blr
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	5:
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	5:
86
	
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	subfic r0, r0, 4
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	subfic r0, r0, 4
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	mtctr r0
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	mtctr r0
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	6:
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	6:
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	lbz r7, 4(r4)
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	lbz r7, 4(r4)
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	addi r4, r4, 1
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	addi r4, r4, 1
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	stb r7, 4(r6)
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	stb r7, 4(r6)
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	addi r6, r6, 1
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	addi r6, r6, 1
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	bdnz 6b
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	bdnz 6b
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	subf r5, r0, r5
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	subf r5, r0, r5
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	rlwinm. r7, r5, 32-3, 3, 31
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	rlwinm. r7, r5, 32-3, 3, 31
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	beq 2b
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	beq 2b
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	mtctr r7
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	mtctr r7
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	b 1b
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	b 1b
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jump_to_kernel:
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jump_to_kernel:
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	# r3 = bootinfo (pa)
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	# r3 = bootinfo (pa)
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	# r4 = bootinfo_size
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	# r4 = bootinfo_size
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	# r5 = trans (pa)
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	# r5 = trans (pa)
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	# r6 = bytes to copy
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	# r6 = bytes to copy
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	# r7 = real_mode (pa)
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	# r7 = real_mode (pa)
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	# r8 = framebuffer (pa)
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	# r9 = scanline
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114
	
112
	# disable interrupts
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	# disable interrupts
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116
	
114
	mfmsr r31
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	mfmsr r31
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	rlwinm r31, r31, 0, 17, 15
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	rlwinm r31, r31, 0, 17, 15
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	mtmsr r31
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	mtmsr r31
117
	
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	# set real_mode meeting point address
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	# set real_mode meeting point address
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122
	
120
	mtspr srr0, r7
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	mtspr srr0, r7
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	# jumps to real_mode
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	# jumps to real_mode
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126
	
124
	mfmsr r31
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	mfmsr r31
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	lis r30, ~0@h
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	lis r30, ~0@h
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	ori r30, r30, ~(msr_ir | msr_dr)@l
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	ori r30, r30, ~(msr_ir | msr_dr | msr_ee)@l
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	and r31, r31, r30
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	and r31, r31, r30
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	mtspr srr1, r31
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	mtspr srr1, r31
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	sync
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	sync
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	isync
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	isync
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	rfi
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	rfi
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.section REALMODE, "ax"
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.section REALMODE, "ax"
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.align PAGE_WIDTH
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.align PAGE_WIDTH
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.global real_mode
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.global real_mode
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138
real_mode:
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real_mode:
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143
	DEBUG_real_mode
139
	
144
	
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	# copy kernel to proper location
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	# copy kernel to proper location
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	#
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	#
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	# r5 = trans (pa)
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	# r5 = trans (pa)
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	# r6 = bytes to copy
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	# r6 = bytes to copy
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149
	# r8 = framebuffer (pa)
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150
	# r9 = scanline
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151
	
145
	li r31, PAGE_SIZE >> 2
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	li r31, PAGE_SIZE >> 2
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	li r30, 0
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	li r30, 0
147
	
154
	
148
	page_copy:
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	page_copy:
149
		
156
		
150
		cmpwi r6, 0
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		cmpwi r6, 0
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		beq copy_end
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		beq copy_end
152
		
159
		
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		# copy page
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		# copy page
154
		
161
		
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		mtctr r31
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		mtctr r31
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		lwz r29, 0(r5)
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		lwz r29, 0(r5)
157
		
164
		
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		copy_loop:
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		copy_loop:
159
			
166
			
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			lwz r28, 0(r29)
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			lwz r28, 0(r29)
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			stw r28, 0(r30)
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			stw r28, 0(r30)
162
			
169
			
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			addi r29, r29, 4
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			addi r29, r29, 4
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			addi r30, r30, 4
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			addi r30, r30, 4
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			subi r6, r6, 4
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			subi r6, r6, 4
166
			
173
			
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			cmpwi r6, 0
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			cmpwi r6, 0
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			beq copy_end
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			beq copy_end
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176
			
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			bdnz copy_loop
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			bdnz copy_loop
171
		
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		addi r5, r5, 4
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		addi r5, r5, 4
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		b page_copy
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		b page_copy
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181
	
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	copy_end:
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	copy_end:
176
	
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177
	# initially fill segment registers
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	# initially fill segment registers
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179
	li r31, 16
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	li r31, 16
180
	mtctr r31
187
	mtctr r31
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	li r31, 0
188
	li r31, 0
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	li r30, 0x2000
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	li r30, 0x2000
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190
 
184
	seg_fill:
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	seg_fill:
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186
		mtsrin r30, r31
193
		mtsrin r30, r31
187
		addi r30, r30, 0x111
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		addi r30, r30, 0x111
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		addis r31, r31, 0x1000    # move to next SR
195
		addis r31, r31, 0x1000    # move to next SR
189
		
196
		
190
		bdnz seg_fill
197
		bdnz seg_fill
191
	
198
	
192
	# invalidate block address translation registers
199
	# invalidate block address translation registers
193
	
200
	
194
	li r30, 0
201
	li r30, 0
195
	
202
	
196
	mtspr ibat0u, r30
203
	mtspr ibat0u, r30
197
	mtspr ibat0l, r30
204
	mtspr ibat0l, r30
198
	
205
	
199
	mtspr ibat1u, r30
206
	mtspr ibat1u, r30
200
	mtspr ibat1l, r30
207
	mtspr ibat1l, r30
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202
	mtspr ibat2u, r30
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	mtspr ibat2u, r30
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	mtspr ibat2l, r30
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	mtspr ibat2l, r30
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205
	mtspr ibat3u, r30
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	mtspr ibat3u, r30
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	mtspr ibat3l, r30
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	mtspr ibat3l, r30
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208
	mtspr dbat0u, r30
215
	mtspr dbat0u, r30
209
	mtspr dbat0l, r30
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	mtspr dbat0l, r30
210
	
217
	
211
	mtspr dbat1u, r30
218
	mtspr dbat1u, r30
212
	mtspr dbat1l, r30
219
	mtspr dbat1l, r30
213
	
220
	
214
	mtspr dbat2u, r30
221
	mtspr dbat2u, r30
215
	mtspr dbat2l, r30
222
	mtspr dbat2l, r30
216
	
223
	
217
	mtspr dbat3u, r30
224
	mtspr dbat3u, r30
218
	mtspr dbat3l, r30
225
	mtspr dbat3l, r30
219
	
226
	
220
	# create identity mapping
227
	# create identity mapping
221
	
228
	
222
	# FIXME: map exactly the size of RAM
229
	# FIXME: map exactly the size of RAM
223
	
230
	
224
	lis r31, 0x8000
231
	lis r31, 0x8000
225
	ori r31, r31, 0x0ffe
232
	ori r31, r31, 0x0ffe
226
	
233
	
227
	lis r30, 0x0000
234
	lis r30, 0x0000
228
	ori r30, r30, 0x0002
235
	ori r30, r30, 0x0002
229
	
236
	
230
	mtspr ibat0u, r31
237
	mtspr ibat0u, r31
231
	mtspr ibat0l, r30
238
	mtspr ibat0l, r30
232
	
239
	
233
	mtspr dbat0u, r31
240
	mtspr dbat0u, r31
234
	mtspr dbat0l, r30
241
	mtspr dbat0l, r30
235
	
242
	
236
	tlbia
243
	tlbia
237
	tlbsync
244
	tlbsync
238
	
245
	
239
	# start the kernel
246
	# start the kernel
240
	#
247
	#
241
	# r3 = bootinfo (pa)
248
	# r3 = bootinfo (pa)
242
	
249
	
243
	lis r31, KERNEL_START_ADDR@ha
250
	lis r31, KERNEL_START_ADDR@ha
244
	addi r31, r31, KERNEL_START_ADDR@l
251
	addi r31, r31, KERNEL_START_ADDR@l
245
	
252
	
246
	mtspr srr0, r31
253
	mtspr srr0, r31
247
	
254
	
248
	mfmsr r31
255
	mfmsr r31
249
	ori r31, r31, (msr_ir | msr_dr)@l
256
	ori r31, r31, (msr_ir | msr_dr)@l
250
	mtspr srr1, r31
257
	mtspr srr1, r31
251
	
258
	
252
	sync
259
	sync
253
	isync
260
	isync
-
 
261
	
-
 
262
	DEBUG_rfi
254
	rfi
263
	rfi
255
 
264
 
256
.align PAGE_WIDTH
265
.align PAGE_WIDTH
257
.global trans
266
.global trans
258
trans:
267
trans:
259
	.space (TRANS_SIZE * TRANS_ITEM_SIZE)
268
	.space (TRANS_SIZE * TRANS_ITEM_SIZE)
260
 
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