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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 25 
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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#
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 28 
 
- 
 
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#include "asm.h"
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#include "regname.h"
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#include "regname.h"
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 31 
 
31 
.data
 32 
.data
32 
 
 33 
 
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flush_buffer:
 34 
flush_buffer:
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	.space (L1_CACHE_LINES * L1_CACHE_BYTES)
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	.space (L1_CACHE_LINES * L1_CACHE_BYTES)
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 36 
 
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.text
 37 
.text
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 38 
 
38 
.global memsetb
 39 
.global halt
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.global memcpy
 - 
 
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.global flush_instruction_cache
 - 
 
41 
.global jump_to_kernel
 40 
.global jump_to_kernel
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 41 
 
43 
memsetb:
 42 
halt:
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	rlwimi r5, r5, 8, 16, 23
 - 
 
45 
	rlwimi r5, r5, 16, 0, 15
 43 
	b halt
46
44 
 
47 
	addi r14, r3, -4
 - 
 
48
- 
 
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	cmplwi 0, r4, 4
 - 
 
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	blt 7f
 - 
 
51
- 
 
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	stwu r5, 4(r14)
 - 
 
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	beqlr
 - 
 
54
- 
 
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	andi. r15, r14, 3
 - 
 
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	add r4, r15, r4
 - 
 
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	subf r14, r15, r14
 - 
 
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	srwi r15, r4, 2
 - 
 
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	mtctr r15
 - 
 
60
- 
 
61 
	bdz 6f
 - 
 
62
- 
 
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	1:
 - 
 
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		stwu r5, 4(r14)
 - 
 
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		bdnz 1b
 - 
 
66
- 
 
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	6:
 - 
 
68
- 
 
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	andi. r4, r4, 3
 - 
 
70
- 
 
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	7:
 - 
 
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- 
 
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	cmpwi 0, r4, 0
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jump_to_kernel:
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	beqlr
 - 
 
75
- 
 
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	mtctr r4
 - 
 
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	addi r6, r6, 3
 - 
 
78
- 
 
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	8:
 - 
 
80
- 
 
81 
	stbu r5, 1(r14)
 - 
 
82 
	bdnz 8b
 - 
 
83
46
- 
 
 47 
	# r3 = memmap (pa)
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	blr
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	# r4 = trans (pa)
- 
 
 49 
	# r5 = number of kernel pages
- 
 
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	# r6 = real_mode (pa)
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 51
86 
memcpy:
 - 
 
87 
	srwi. r7, r5, 3
 - 
 
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	addi r6, r3, -4
 - 
 
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	addi r4, r4, -4
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	mtspr srr0, r6
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	beq	2f
 - 
 
91
53
92 
	andi. r0, r6, 3
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	# jumps to real_mode
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	mtctr r7
 - 
 
94 
	bne 5f
 - 
 
95
55
- 
 
 56 
	mfmsr r31
- 
 
 57 
	lis r30, ~0@h
- 
 
 58 
	ori r30, r30, ~(msr_ir | msr_dr)@l
- 
 
 59 
	and r31, r31, r30
- 
 
 60 
	mtspr srr1, r31
96 
	1:
 61 
	rfi
97
62 
 
98 
	lwz r7, 4(r4)
 63 
.section REALMODE
99 
	lwzu r8, 8(r4)
 64 
.align PAGE_WIDTH
100 
	stw r7, 4(r6)
 - 
 
101 
	stwu r8, 8(r6)
 65 
.global real_mode
102 
	bdnz 1b
 - 
 
103
66 
 
104 
	andi. r5, r5, 7
 67 
real_mode:
105
68
- 
 
 69 
	# copy kernel to proper location
106 
	2:
 70 
	#
- 
 
 71 
	# r4 = trans (pa)
- 
 
 72 
	# r5 = number of kernel pages
107
73
108 
	cmplwi 0, r5, 4
 74 
	li r31, PAGE_SIZE >> 3
109 
	blt 3f
 75 
	li r30, 0
110
76
111 
	lwzu r0, 4(r4)
 - 
 
112 
	addi r5, r5, -4
 - 
 
113 
	stwu r0, 4(r6)
 77 
	page_copy:
114
78
115 
	3:
 79 
		cmpwi r5, 0
- 
 
 80 
		beq copy_end
116
81
117 
	cmpwi 0, r5, 0
 82 
		# copy single page
118 
	beqlr
 - 
 
119 
	mtctr r5
 - 
 
120 
	addi r4, r4, 3
 - 
 
121 
	addi r6, r6, 3
 - 
 
122
83
123 
	4:
 84 
		mtctr r31
- 
 
 85 
		lwz r29, 0(r4)
124
86
125 
	lbzu r0, 1(r4)
 - 
 
126 
	stbu r0, 1(r6)
 87 
		copy_loop:
127 
	bdnz 4b
 - 
 
128 
	blr
 - 
 
129
88
- 
 
 89 
			lwz r28, 0(r29)
130 
	5:
 90 
			stw r28, 0(r30)
131
91
132 
	subfic r0, r0, 4
 92 
			addi r29, r29, 4
133 
	mtctr r0
 93 
			addi r30, r30, 4
134
94
135 
	6:
 95 
			bdnz copy_loop
136
96
137 
	lbz r7, 4(r4)
 - 
 
138 
	addi r4, r4, 1
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		subi r5, r5, 1
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	stb r7, 4(r6)
 - 
 
140 
	addi r6, r6, 1
 98 
		addi r4, r4, 4
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	bdnz 6b
 - 
 
142 
	subf r5, r0, r5
 99 
		b page_copy
143 
	rlwinm. r7, r5, 32-3, 3, 31
 - 
 
144 
	beq 2b
 - 
 
145 
	mtctr r7
 - 
 
146 
	b 1b
 - 
 
147
100
148 
flush_instruction_cache:
 101 
	copy_end:
149 
 
 102
150 
	# Flush data cache
 103 
	# fill segment registers
151
104 
 
152 
	lis r3, flush_buffer@h
 105 
	li r31, 16
153 
	ori r3, r3, flush_buffer@l
 106 
	mtctr r31
154 
	li r4, L1_CACHE_LINES
 107 
	li r31, 0
155 
	mtctr r4
 108 
	li r30, 0x2000
156
109
157 
	0:
 110 
	seg_fill:
158
111
159 
	lwz r4, 0(r3)
 112 
		mtsrin r30, r31
160 
	addi r3, r3, L1_CACHE_BYTES
 - 
 
161 
	bdnz 0b
 - 
 
162
113
- 
 
 114 
		addis r31, r31, 0x1000    # add 256 MB
163 
	# Invalidate instruction cache
 115 
		addi  r30, r30, 0x111     # move to next SR
164
116
165 
	li r3, 0
 - 
 
166 
	ori	r3, r3, (hid0_ice | hid0_dce | hid0_icfi | hid0_dci)
 - 
 
167 
	mfspr r4, hid0
 117 
		bdnz seg_fill
168 
	or r5, r4, r3
 - 
 
169 
	isync
 - 
 
170 
	mtspr hid0, r5
 - 
 
171 
	sync
 - 
 
172 
	isync
 - 
 
173
118
174 
	# Enable instruction cache
 119 
	# create identity mapping
175
120
176 
	ori	r5, r4, hid0_ice
 - 
 
177 
	mtspr hid0, r5
 - 
 
178 
	sync
 - 
 
179 
	isync
 - 
 
180 
	blr
 121 
	tlbia
181 
 
 122
182 
jump_to_kernel:
 123 
	# start the kernel
- 
 
 124 
	#
- 
 
 125 
	# r3 = memmap (pa)
183
126
184 
	# r3 = kernel_start (va)
 127 
	lis r31, KERNEL_START_ADDR@ha
185 
	# r4 = memmap (pa)
 - 
 
186 
	# r5 = real_mode (pa)
 128 
	addi r31, r31, KERNEL_START_ADDR@l
187
129
188 
	mtspr srr0, r5
 130 
	mtspr srr0, r31
189
131
- 
 
 132 
	mfmsr r31
- 
 
 133 
	ori r31, r31, (msr_ir | msr_dr)@l
190 
	# jumps to real_mode
 134 
	mtspr srr1, r31
191
135
192 
	mfmsr r5
 - 
 
193 
	lis r6, ~0@h
 - 
 
194 
	ori r6, r6, ~(msr_ir | msr_dr)@l
 - 
 
195 
	and r5, r5, r6
 - 
 
196 
	mtspr srr1, r5
 - 
 
197 
	rfi
 136 
	rfi
198 
 
 137 
 
199 
.section REALMODE
 - 
 
200 
.align 12
 138 
.align PAGE_WIDTH
201 
.global real_mode
 139 
.global trans
202 
 
 - 
 
203 
real_mode:
 140 
trans:
204 
 
 - 
 
205 
	# fill segment registers
 - 
 
206 
 
 - 
 
207 
	li r5, 16
 - 
 
208 
	mtctr r5
 - 
 
209 
	li r5, 0
 - 
 
210 
	li r6, 0
 - 
 
211
- 
 
212 
	seg_fill:
 - 
 
213
- 
 
214 
		mtsrin r6, r5
 - 
 
215 
		addis r5, r5, 0x1000    # move to next SR
 141 
	.space (TRANS_SIZE * TRANS_ITEM_SIZE)
216 
		addis r6, r6, 0x10      # add 256 MB, move to next SR
 - 
 
217
- 
 
218 
		bdnz seg_fill
 - 
 
219
- 
 
220 
	# bootstrap kernel
 - 
 
221 
	#
 - 
 
222 
	# r3 = kernel_start (va)
 - 
 
223 
	# r4 = memmap (pa)       -> r10
 - 
 
224
- 
 
225 
	mtspr srr0, r3
 - 
 
226
- 
 
227 
	mfmsr r5
 - 
 
228 
	ori r5, r5, (msr_ir | msr_dr)@l
 - 
 
229 
	mtspr srr1, r5
 - 
 
230
- 
 
231 
	mr r10, r4
 - 
 
232 
	rfi
 -