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Rev 1003 Rev 1022
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#
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#
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# Copyright (C) 2006 Martin Decky
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# Copyright (C) 2006 Martin Decky
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# All rights reserved.
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# All rights reserved.
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#
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#
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# Redistribution and use in source and binary forms, with or without
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions
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# modification, are permitted provided that the following conditions
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# are met:
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# are met:
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#
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#
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# - Redistributions of source code must retain the above copyright
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# - Redistributions of source code must retain the above copyright
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#   notice, this list of conditions and the following disclaimer.
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#   notice, this list of conditions and the following disclaimer.
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# - Redistributions in binary form must reproduce the above copyright
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# - Redistributions in binary form must reproduce the above copyright
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#   notice, this list of conditions and the following disclaimer in the
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#   notice, this list of conditions and the following disclaimer in the
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#   documentation and/or other materials provided with the distribution.
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#   documentation and/or other materials provided with the distribution.
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# - The name of the author may not be used to endorse or promote products
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# - The name of the author may not be used to endorse or promote products
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#   derived from this software without specific prior written permission.
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#   derived from this software without specific prior written permission.
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#
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#
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# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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#
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#include "regname.h"
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#include "regname.h"
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.data
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.data
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flush_buffer:
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flush_buffer:
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	.space (L1_CACHE_LINES * L1_CACHE_BYTES)
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	.space (L1_CACHE_LINES * L1_CACHE_BYTES)
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.text
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.text
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.global memsetb
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.global memsetb
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.global memcpy
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.global memcpy
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.global flush_instruction_cache
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.global flush_instruction_cache
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.global jump_to_kernel
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.global jump_to_kernel
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memsetb:
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memsetb:
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	rlwimi r5, r5, 8, 16, 23
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	rlwimi r5, r5, 8, 16, 23
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	rlwimi r5, r5, 16, 0, 15
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	rlwimi r5, r5, 16, 0, 15
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	addi r14, r3, -4
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	addi r14, r3, -4
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	cmplwi 0, r4, 4
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	cmplwi 0, r4, 4
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	blt 7f
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	blt 7f
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	stwu r5, 4(r14)
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	stwu r5, 4(r14)
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	beqlr
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	beqlr
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	andi. r15, r14, 3
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	andi. r15, r14, 3
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	add r4, r15, r4
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	add r4, r15, r4
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	subf r14, r15, r14
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	subf r14, r15, r14
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	srwi r15, r4, 2
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	srwi r15, r4, 2
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	mtctr r15
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	mtctr r15
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	bdz 6f
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	bdz 6f
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	1:
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	1:
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		stwu r5, 4(r14)
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		stwu r5, 4(r14)
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		bdnz 1b
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		bdnz 1b
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	6:
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	6:
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	andi. r4, r4, 3
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	andi. r4, r4, 3
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	7:
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	7:
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	cmpwi 0, r4, 0
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	cmpwi 0, r4, 0
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	beqlr
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	beqlr
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	mtctr r4
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	mtctr r4
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	addi r6, r6, 3
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	addi r6, r6, 3
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	8:
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	8:
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	stbu r5, 1(r14)
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	stbu r5, 1(r14)
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	bdnz 8b
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	bdnz 8b
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	blr
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	blr
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memcpy:
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memcpy:
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	srwi. r7, r5, 3
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	srwi. r7, r5, 3
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	addi r6, r3, -4
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	addi r6, r3, -4
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	addi r4, r4, -4
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	addi r4, r4, -4
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	beq	2f
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	beq	2f
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	andi. r0, r6, 3
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	andi. r0, r6, 3
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	mtctr r7
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	mtctr r7
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	bne 5f
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	bne 5f
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	1:
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	1:
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	lwz r7, 4(r4)
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	lwz r7, 4(r4)
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	lwzu r8, 8(r4)
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	lwzu r8, 8(r4)
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	stw r7, 4(r6)
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	stw r7, 4(r6)
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	stwu r8, 8(r6)
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	stwu r8, 8(r6)
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	bdnz 1b
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	bdnz 1b
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	andi. r5, r5, 7
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	andi. r5, r5, 7
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	2:
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	2:
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	cmplwi 0, r5, 4
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	cmplwi 0, r5, 4
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	blt 3f
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	blt 3f
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	lwzu r0, 4(r4)
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	lwzu r0, 4(r4)
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	addi r5, r5, -4
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	addi r5, r5, -4
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	stwu r0, 4(r6)
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	stwu r0, 4(r6)
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	3:
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	3:
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	cmpwi 0, r5, 0
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	cmpwi 0, r5, 0
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	beqlr
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	beqlr
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	mtctr r5
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	mtctr r5
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	addi r4, r4, 3
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	addi r4, r4, 3
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	addi r6, r6, 3
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	addi r6, r6, 3
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	4:
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	4:
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	lbzu r0, 1(r4)
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	lbzu r0, 1(r4)
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	stbu r0, 1(r6)
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	stbu r0, 1(r6)
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	bdnz 4b
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	bdnz 4b
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	blr
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	blr
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	5:
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	5:
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	subfic r0, r0, 4
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	subfic r0, r0, 4
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	mtctr r0
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	mtctr r0
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	6:
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	6:
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	lbz r7, 4(r4)
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	lbz r7, 4(r4)
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	addi r4, r4, 1
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	addi r4, r4, 1
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	stb r7, 4(r6)
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	stb r7, 4(r6)
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	addi r6, r6, 1
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	addi r6, r6, 1
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	bdnz 6b
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	bdnz 6b
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	subf r5, r0, r5
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	subf r5, r0, r5
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	rlwinm. r7, r5, 32-3, 3, 31
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	rlwinm. r7, r5, 32-3, 3, 31
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	beq 2b
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	beq 2b
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	mtctr r7
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	mtctr r7
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	b 1b
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	b 1b
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flush_instruction_cache:
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flush_instruction_cache:
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	# Flush data cache
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	# Flush data cache
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	lis r3, flush_buffer@h
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	lis r3, flush_buffer@h
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	ori r3, r3, flush_buffer@l
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	ori r3, r3, flush_buffer@l
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	li r4, L1_CACHE_LINES
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	li r4, L1_CACHE_LINES
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	mtctr r4
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	mtctr r4
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	0:
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	0:
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	lwz r4, 0(r3)
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	lwz r4, 0(r3)
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	addi r3, r3, L1_CACHE_BYTES
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	addi r3, r3, L1_CACHE_BYTES
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	bdnz 0b
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	bdnz 0b
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	# Invalidate instruction cache
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	# Invalidate instruction cache
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	li r3, 0
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	li r3, 0
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	ori	r3, r3, (hid0_ice | hid0_dce | hid0_icfi | hid0_dci)
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	ori	r3, r3, (hid0_ice | hid0_dce | hid0_icfi | hid0_dci)
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	mfspr r4, hid0
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	mfspr r4, hid0
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	or r5, r4, r3
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	or r5, r4, r3
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	isync
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	isync
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	mtspr hid0, r5
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	mtspr hid0, r5
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	sync
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	sync
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	isync
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	isync
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	# Enable instruction cache
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	# Enable instruction cache
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	ori	r5, r4, hid0_ice
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	ori	r5, r4, hid0_ice
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	mtspr hid0, r5
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	mtspr hid0, r5
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	sync
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	sync
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	isync
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	isync
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	blr
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	blr
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jump_to_kernel:
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jump_to_kernel:
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	# r3 = kernel_start (va)
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	# r4 = memmap (pa)
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	# r5 = real_mode (pa)
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	mtspr srr0, r5
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	# jumps to real_mode
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- 
 
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	mfmsr r5
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	lis r6, ~0@h
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	ori r6, r6, ~(msr_ir | msr_dr)@l
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	and r5, r5, r6
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	mtspr srr1, r5
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	rfi
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.section REALMODE
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.align 12
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.global real_mode
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real_mode:
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	# fill segment registers
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	li r5, 16
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	mtctr r5
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	li r5, 0
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	li r6, 0
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- 
 
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	seg_fill:
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		mtsrin r6, r5
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		addis r5, r5, 0x1000    # move to next SR
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		addis r6, r6, 0x10      # add 256 MB, move to next SR
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		bdnz seg_fill
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	# bootstrap kernel
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	#
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	# r3 = kernel_start (va)
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	# r4 = memmap (pa)       -> r10
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	mtspr srr0, r3
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	mfmsr r5
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	ori r5, r5, (msr_ir | msr_dr)@l
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	mtspr srr1, r5
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	mr r10, r4
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	mr r10, r4
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	mtlr r3
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	blr
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	rfi
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