WebSVN – HelenOS-historic – Diff – /boot/trunk/arch/ppc32/loader/asm.S


#
# Copyright (C) 2006 Martin Decky
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions
# are met:
#
# - Redistributions of source code must retain the above copyright
#   notice, this list of conditions and the following disclaimer.
# - Redistributions in binary form must reproduce the above copyright
#   notice, this list of conditions and the following disclaimer in the
#   documentation and/or other materials provided with the distribution.
# - The name of the author may not be used to endorse or promote products
#   derived from this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
 
#include "regname.h"
 
 
.data
 
flush_buffer:
	.space (L1_CACHE_LINES * L1_CACHE_BYTES)
 
.text
 
.global memsetb
.global memcpy
.global flush_instruction_cache
.global jump_to_kernel
 
memsetb:
	rlwimi r5, r5, 8, 16, 23
	rlwimi r5, r5, 16, 0, 15
	
	addi r14, r3, -4
	
	cmplwi 0, r4, 4
	blt 7f
	
	stwu r5, 4(r14)
	beqlr
	
	andi. r15, r14, 3
	add r4, r15, r4
	subf r14, r15, r14
	srwi r15, r4, 2
	mtctr r15
	
	bdz 6f
	
	1:
		stwu r5, 4(r14)
		bdnz 1b
	
	6:
	
	andi. r4, r4, 3
	
	7:
	
	cmpwi 0, r4, 0
	beqlr
	
	mtctr r4
	addi r6, r6, 3
	
	8:
	
	stbu r5, 1(r14)
	bdnz 8b
	
	blr
 
memcpy:
	srwi. r7, r5, 3
	addi r6, r3, -4
	addi r4, r4, -4
	beq	2f
	
	andi. r0, r6, 3
	mtctr r7
	bne 5f
	
	1:
	
	lwz r7, 4(r4)
	lwzu r8, 8(r4)
	stw r7, 4(r6)
	stwu r8, 8(r6)
	bdnz 1b
	
	andi. r5, r5, 7
	
	2:
	
	cmplwi 0, r5, 4
	blt 3f
	
	lwzu r0, 4(r4)
	addi r5, r5, -4
	stwu r0, 4(r6)
	
	3:
	
	cmpwi 0, r5, 0
	beqlr
	mtctr r5
	addi r4, r4, 3
	addi r6, r6, 3
	
	4:
	
	lbzu r0, 1(r4)
	stbu r0, 1(r6)
	bdnz 4b
	blr
	
	5:
	
	subfic r0, r0, 4
	mtctr r0
	
	6:
	
	lbz r7, 4(r4)
	addi r4, r4, 1
	stb r7, 4(r6)
	addi r6, r6, 1
	bdnz 6b
	subf r5, r0, r5
	rlwinm. r7, r5, 32-3, 3, 31
	beq 2b
	mtctr r7
	b 1b
	
flush_instruction_cache:
 
	# Flush data cache
	
	lis r3, flush_buffer@h
	ori r3, r3, flush_buffer@l
	li r4, L1_CACHE_LINES
	mtctr r4
	
	0:
	
	lwz r4, 0(r3)
	addi r3, r3, L1_CACHE_BYTES
	bdnz 0b
	
	# Invalidate instruction cache
	
	li r3, 0
	ori	r3, r3, (hid0_ice | hid0_dce | hid0_icfi | hid0_dci)
	mfspr r4, hid0
	or r5, r4, r3
	isync
	mtspr hid0, r5
	sync
	isync
	
	# Enable instruction cache
	
	ori	r5, r4, hid0_ice
	mtspr hid0, r5
	sync
	isync
	blr
 
jump_to_kernel:
	mr r10, r4
	mtlr r3
	blr
 
 

Rev 964	Rev 1003
1	#	1	#
2	# Copyright (C) 2006 Martin Decky	2	# Copyright (C) 2006 Martin Decky
3	# All rights reserved.	3	# All rights reserved.
4	#	4	#
5	# Redistribution and use in source and binary forms, with or without	5	# Redistribution and use in source and binary forms, with or without
6	# modification, are permitted provided that the following conditions	6	# modification, are permitted provided that the following conditions
7	# are met:	7	# are met:
8	#	8	#
9	# - Redistributions of source code must retain the above copyright	9	# - Redistributions of source code must retain the above copyright
10	# notice, this list of conditions and the following disclaimer.	10	# notice, this list of conditions and the following disclaimer.
11	# - Redistributions in binary form must reproduce the above copyright	11	# - Redistributions in binary form must reproduce the above copyright
12	# notice, this list of conditions and the following disclaimer in the	12	# notice, this list of conditions and the following disclaimer in the
13	# documentation and/or other materials provided with the distribution.	13	# documentation and/or other materials provided with the distribution.
14	# - The name of the author may not be used to endorse or promote products	14	# - The name of the author may not be used to endorse or promote products
15	# derived from this software without specific prior written permission.	15	# derived from this software without specific prior written permission.
16	#	16	#
17	# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	17	# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18	# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	18	# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19	# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	19	# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20	# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	20	# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21	# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	21	# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22	# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	22	# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23	# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	23	# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24	# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	24	# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25	# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	25	# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26	# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	26	# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27	#	27	#
28		28
29	#include "regname.h"	29	#include "regname.h"
30	#include "spr.h"	-
31		30
32	.data	31	.data
33		32
34	flush_buffer:	33	flush_buffer:
35	.space (L1_CACHE_LINES * L1_CACHE_BYTES)	34	.space (L1_CACHE_LINES * L1_CACHE_BYTES)
36		35
37	.text	36	.text
38		37
39	.global memsetb	38	.global memsetb
40	.global memcpy	39	.global memcpy
41	.global flush_instruction_cache	40	.global flush_instruction_cache
42	.global jump_to_kernel	41	.global jump_to_kernel
43		42
44	memsetb:	43	memsetb:
45	rlwimi r5, r5, 8, 16, 23	44	rlwimi r5, r5, 8, 16, 23
46	rlwimi r5, r5, 16, 0, 15	45	rlwimi r5, r5, 16, 0, 15
47		46
48	addi r14, r3, -4	47	addi r14, r3, -4
49		48
50	cmplwi 0, r4, 4	49	cmplwi 0, r4, 4
51	blt 7f	50	blt 7f
52		51
53	stwu r5, 4(r14)	52	stwu r5, 4(r14)
54	beqlr	53	beqlr
55		54
56	andi. r15, r14, 3	55	andi. r15, r14, 3
57	add r4, r15, r4	56	add r4, r15, r4
58	subf r14, r15, r14	57	subf r14, r15, r14
59	srwi r15, r4, 2	58	srwi r15, r4, 2
60	mtctr r15	59	mtctr r15
61		60
62	bdz 6f	61	bdz 6f
63		62
64	1:	63	1:
65	stwu r5, 4(r14)	64	stwu r5, 4(r14)
66	bdnz 1b	65	bdnz 1b
67		66
68	6:	67	6:
69		68
70	andi. r4, r4, 3	69	andi. r4, r4, 3
71		70
72	7:	71	7:
73		72
74	cmpwi 0, r4, 0	73	cmpwi 0, r4, 0
75	beqlr	74	beqlr
76		75
77	mtctr r4	76	mtctr r4
78	addi r6, r6, 3	77	addi r6, r6, 3
79		78
80	8:	79	8:
81		80
82	stbu r5, 1(r14)	81	stbu r5, 1(r14)
83	bdnz 8b	82	bdnz 8b
84		83
85	blr	84	blr
86		85
87	memcpy:	86	memcpy:
88	srwi. r7, r5, 3	87	srwi. r7, r5, 3
89	addi r6, r3, -4	88	addi r6, r3, -4
90	addi r4, r4, -4	89	addi r4, r4, -4
91	beq 2f	90	beq 2f
92		91
93	andi. r0, r6, 3	92	andi. r0, r6, 3
94	mtctr r7	93	mtctr r7
95	bne 5f	94	bne 5f
96		95
97	1:	96	1:
98		97
99	lwz r7, 4(r4)	98	lwz r7, 4(r4)
100	lwzu r8, 8(r4)	99	lwzu r8, 8(r4)
101	stw r7, 4(r6)	100	stw r7, 4(r6)
102	stwu r8, 8(r6)	101	stwu r8, 8(r6)
103	bdnz 1b	102	bdnz 1b
104		103
105	andi. r5, r5, 7	104	andi. r5, r5, 7
106		105
107	2:	106	2:
108		107
109	cmplwi 0, r5, 4	108	cmplwi 0, r5, 4
110	blt 3f	109	blt 3f
111		110
112	lwzu r0, 4(r4)	111	lwzu r0, 4(r4)
113	addi r5, r5, -4	112	addi r5, r5, -4
114	stwu r0, 4(r6)	113	stwu r0, 4(r6)
115		114
116	3:	115	3:
117		116
118	cmpwi 0, r5, 0	117	cmpwi 0, r5, 0
119	beqlr	118	beqlr
120	mtctr r5	119	mtctr r5
121	addi r4, r4, 3	120	addi r4, r4, 3
122	addi r6, r6, 3	121	addi r6, r6, 3
123		122
124	4:	123	4:
125		124
126	lbzu r0, 1(r4)	125	lbzu r0, 1(r4)
127	stbu r0, 1(r6)	126	stbu r0, 1(r6)
128	bdnz 4b	127	bdnz 4b
129	blr	128	blr
130		129
131	5:	130	5:
132		131
133	subfic r0, r0, 4	132	subfic r0, r0, 4
134	mtctr r0	133	mtctr r0
135		134
136	6:	135	6:
137		136
138	lbz r7, 4(r4)	137	lbz r7, 4(r4)
139	addi r4, r4, 1	138	addi r4, r4, 1
140	stb r7, 4(r6)	139	stb r7, 4(r6)
141	addi r6, r6, 1	140	addi r6, r6, 1
142	bdnz 6b	141	bdnz 6b
143	subf r5, r0, r5	142	subf r5, r0, r5
144	rlwinm. r7, r5, 32-3, 3, 31	143	rlwinm. r7, r5, 32-3, 3, 31
145	beq 2b	144	beq 2b
146	mtctr r7	145	mtctr r7
147	b 1b	146	b 1b
148		147
149	flush_instruction_cache:	148	flush_instruction_cache:
150		149
151	# Flush data cache	150	# Flush data cache
152		151
153	lis r3, flush_buffer@h	152	lis r3, flush_buffer@h
154	ori r3, r3, flush_buffer@l	153	ori r3, r3, flush_buffer@l
155	li r4, L1_CACHE_LINES	154	li r4, L1_CACHE_LINES
156	mtctr r4	155	mtctr r4
157		156
158	0:	157	0:
159		158
160	lwz r4, 0(r3)	159	lwz r4, 0(r3)
161	addi r3, r3, L1_CACHE_BYTES	160	addi r3, r3, L1_CACHE_BYTES
162	bdnz 0b	161	bdnz 0b
163		162
164	# Invalidate instruction cache	163	# Invalidate instruction cache
165		164
166	li r3, 0	165	li r3, 0
167	ori r3, r3, (HID0_ICE \| HID0_DCE \| HID0_ICFI \| HID0_DCI)	166	ori r3, r3, (hid0_ice \| hid0_dce \| hid0_icfi \| hid0_dci)
168	mfspr r4, SPRN_HID0	167	mfspr r4, hid0
169	or r5, r4, r3	168	or r5, r4, r3
170	isync	169	isync
171	mtspr SPRN_HID0, r5	170	mtspr hid0, r5
172	sync	171	sync
173	isync	172	isync
174		173
175	# Enable instruction cache	174	# Enable instruction cache
176		175
177	ori r5, r4, HID0_ICE	176	ori r5, r4, hid0_ice
178	mtspr SPRN_HID0, r5	177	mtspr hid0, r5
179	sync	178	sync
180	isync	179	isync
181	blr	180	blr
182		181
183	jump_to_kernel:	182	jump_to_kernel:
184	mr r10, r4	183	mr r10, r4
185	mtlr r3	184	mtlr r3
186	blr	185	blr
187		-
188		186

Subversion Repositories HelenOS-historic

(root)/boot/trunk/arch/ppc32/loader/asm.S – Rev 964 → 1003