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#define __ppc32_ASM_H__
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#define __ppc32_ASM_H__
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#include <arch/types.h>
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#include <arch/types.h>
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#include <config.h>
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#include <config.h>
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/** Set priority level low
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/** Enable interrupts.
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 *
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 *
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 * Enable interrupts and return previous
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 * Enable interrupts and return previous
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 * value of EE.
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 * value of EE.
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 *
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 * @return Old interrupt priority level.
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 */
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 */
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static inline pri_t cpu_priority_low(void) {
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static inline ipl_t interrupts_enable(void) {
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    pri_t v;
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    ipl_t v;
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    pri_t tmp;
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    ipl_t tmp;
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    __asm__ volatile (
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    __asm__ volatile (
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        "mfmsr %0\n"
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        "mfmsr %0\n"
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        "mfmsr %1\n"
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        "mfmsr %1\n"
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        "ori %1, %1, 1 << 15\n"
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        "ori %1, %1, 1 << 15\n"
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        : "=r" (v), "=r" (tmp)
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        : "=r" (v), "=r" (tmp)
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    );
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    );
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    return v;
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    return v;
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}
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}
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/** Set priority level high
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/** Disable interrupts.
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 *
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 *
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 * Disable interrupts and return previous
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 * Disable interrupts and return previous
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 * value of EE.
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 * value of EE.
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 *
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 * @return Old interrupt priority level.
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 */
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 */
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static inline pri_t cpu_priority_high(void) {
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static inline ipl_t interrupts_disable(void) {
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    pri_t v;
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    ipl_t v;
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    pri_t tmp;
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    ipl_t tmp;
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    __asm__ volatile (
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    __asm__ volatile (
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        "mfmsr %0\n"
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        "mfmsr %0\n"
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        "mfmsr %1\n"
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        "mfmsr %1\n"
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        "rlwinm %1, %1, 0, 17, 15\n"
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        "rlwinm %1, %1, 0, 17, 15\n"
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        : "=r" (v), "=r" (tmp)
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        : "=r" (v), "=r" (tmp)
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    );
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    );
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    return v;
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    return v;
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}
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}
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/** Restore priority level
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/** Restore interrupt priority level.
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 *
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 *
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 * Restore EE.
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 * Restore EE.
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 *
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 * @param ipl Saved interrupt priority level.
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 */
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 */
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static inline void cpu_priority_restore(pri_t pri) {
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static inline void interrupts_restore(ipl_t ipl) {
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    pri_t tmp;
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    ipl_t tmp;
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    __asm__ volatile (
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    __asm__ volatile (
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        "mfmsr %1\n"
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        "mfmsr %1\n"
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        "rlwimi  %0, %1, 0, 17, 15\n"
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        "rlwimi  %0, %1, 0, 17, 15\n"
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        "cmpw 0, %0, %1\n"
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        "cmpw 0, %0, %1\n"
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        "beq 0f\n"
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        "beq 0f\n"
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        "mtmsr %0\n"
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        "mtmsr %0\n"
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        "0:\n"
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        "0:\n"
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        : "=r" (pri), "=r" (tmp)
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        : "=r" (ipl), "=r" (tmp)
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        : "0" (pri)
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        : "0" (ipl)
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    );
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    );
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}
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}
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/** Return raw priority level
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/** Return interrupt priority level.
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 *
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 *
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 * Return EE.
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 * Return EE.
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 *
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 * @return Current interrupt priority level.
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 */
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 */
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static inline pri_t cpu_priority_read(void) {
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static inline ipl_t interrupts_read(void) {
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    pri_t v;
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    ipl_t v;
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    __asm__ volatile (
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    __asm__ volatile (
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        "mfmsr %0\n"
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        "mfmsr %0\n"
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        : "=r" (v)
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        : "=r" (v)
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    );
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    );
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    return v;
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    return v;