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| Rev 403 | Rev 413 | ||
|---|---|---|---|
| Line 313... | Line 313... | ||
| 313 | * @param asid ASID. |
313 | * @param asid ASID. |
| 314 | */ |
314 | */ |
| 315 | void tlb_invalidate(asid_t asid) |
315 | void tlb_invalidate(asid_t asid) |
| 316 | { |
316 | { |
| 317 | entry_hi_t hi; |
317 | entry_hi_t hi; |
| 318 | pri_t pri; |
318 | ipl_t ipl; |
| 319 | int i; |
319 | int i; |
| 320 | 320 | ||
| 321 | ASSERT(asid != ASID_INVALID); |
321 | ASSERT(asid != ASID_INVALID); |
| 322 | 322 | ||
| 323 | pri = cpu_priority_high(); |
323 | ipl = interrupts_disable(); |
| 324 | 324 | ||
| 325 | for (i = 0; i < TLB_SIZE; i++) { |
325 | for (i = 0; i < TLB_SIZE; i++) { |
| 326 | cp0_index_write(i); |
326 | cp0_index_write(i); |
| 327 | tlbr(); |
327 | tlbr(); |
| 328 | 328 | ||
| Line 334... | Line 334... | ||
| 334 | cp0_entry_lo1_write(0); |
334 | cp0_entry_lo1_write(0); |
| 335 | tlbwi(); |
335 | tlbwi(); |
| 336 | } |
336 | } |
| 337 | } |
337 | } |
| 338 | 338 | ||
| 339 | cpu_priority_restore(pri); |
339 | interrupts_restore(ipl); |
| 340 | } |
340 | } |
| 341 | 341 | ||
| 342 | /** Try to find PTE for faulting address |
342 | /** Try to find PTE for faulting address |
| 343 | * |
343 | * |
| 344 | * Try to find PTE for faulting address. |
344 | * Try to find PTE for faulting address. |