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#include <arch/types.h>
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#include <arch/types.h>
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#define cp0_status_ie_enabled_bit   (1<<0)
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#define cp0_status_ie_enabled_bit   (1<<0)
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#define cp0_status_exl_exception_bit    (1<<1)
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#define cp0_status_exl_exception_bit    (1<<1)
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#define cp0_status_erl_error_bit    (1<<2)
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#define cp0_status_erl_error_bit    (1<<2)
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#define cp0_status_bev_bootstrap_bit    (1<<22)
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#define cp0_status_um_bit           (1<<4)
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#define cp0_status_um_bit           (1<<4)
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#define cp0_status_bev_bootstrap_bit    (1<<22)
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#define cp0_status_fpu_bit              (1<<29)
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#define cp0_status_im7_shift        15
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#define cp0_status_im7_shift        15
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/*
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/*
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 * Magic value for use in msim.
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 * Magic value for use in msim.
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 * On AMD Duron 800Mhz, this roughly seems like one us.
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 * On AMD Duron 800Mhz, this roughly seems like one us.
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 */
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 */
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#define cp0_compare_value       10000
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#define cp0_compare_value       10000
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static inline void tlbp(void)
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{
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    __asm__ volatile ("tlbp");
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}
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static inline void tlbr(void)
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{
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    __asm__ volatile ("tlbr");
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}
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static inline void tlbwi(void)
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{
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    __asm__ volatile ("tlbwi");
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}
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static inline void tlbwr(void)
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{
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    __asm__ volatile ("tlbwr");
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}
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extern  __u32 cp0_index_read(void);
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extern  __u32 cp0_index_read(void);
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extern void cp0_idnex_write(__u32 val);
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extern void cp0_idnex_write(__u32 val);
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extern __u32 cp0_random_read(void);
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extern __u32 cp0_random_read(void);
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extern __u32 cp0_epc_read(void);
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extern __u32 cp0_epc_read(void);
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extern void cp0_epc_write(__u32 val);
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extern void cp0_epc_write(__u32 val);
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extern __u32 cp0_prid_read(void);
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extern __u32 cp0_prid_read(void);
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extern void tlbp(void);
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extern void tlbr(void);
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extern void tlbwi(void);
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extern void tlbwr(void);
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#endif
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#endif