WebSVN – HelenOS-doc – Diff – /design/trunk/src/ch_memory_management.xml

       structure that contains number of references and data used by buddy
       system.</para>
     </section>
     <section id="frame_allocator">
+      <indexterm>
+        <primary>frame allocator</primary>
+      </indexterm>
       <title>Frame allocator</title>
       <para>The frame allocator satisfies kernel requests to allocate
       power-of-two sized blocks of physical memory. Because of zonal
       organization of physical memory, the frame allocator is always working
         to take care of deallocation within the zone's buddy system.</para>
       </formalpara>
     </section>
     <section id="buddy_allocator">
+      <indexterm>
+        <primary>buddy system</primary>
+      </indexterm>
       <title>Buddy allocator</title>
       <para>In the buddy system, the memory is broken down into power-of-two
       sized naturally aligned blocks. These blocks are organized in an array
       of lists, in which the list with index i contains all unallocated blocks
         </formalpara>
       </section>
     </section>
     <section id="slab">
+      <indexterm>
+        <primary>slab allocator</primary>
+      </indexterm>
       <title>Slab allocator</title>
       <para>The majority of memory allocation requests in the kernel is for
       small, frequently used data structures. The basic idea behind the slab
       allocator is that commonly used objects are preallocated in continuous
           paragraph.</para>
         </footnote>. Due to the fact that the sizes of the requested and
       allocated object match, the slab allocator significantly reduces
       internal fragmentation.</para>
+      <indexterm>
+        <primary>slab allocator</primary>
+        <secondary>slab cache</secondary>
+      </indexterm>
       <para>Slabs of one object type are organized in a structure called slab
       cache. There are ususally more slabs in the slab cache, depending on
       previous allocations. If the the slab cache runs out of available slabs,
       new slabs are allocated. In order to exploit parallelism and to avoid
       locking of shared spinlocks, slab caches can have variants of
       processor-private slabs called magazines. On each processor, there is a
       two-magazine cache. Full magazines that are not part of any
       per-processor magazine cache are stored in a global list of full
       magazines.</para>
+      <indexterm>
+        <primary>slab allocator</primary>
+        <secondary>magazine</secondary>
+      </indexterm>
       <para>Each object begins its life in a slab. When it is allocated from
       there, the slab allocator calls a constructor that is registered in the
       respective slab cache. The constructor initializes and brings the object
       into a known state. The object is then used by the user. When the user
       later frees the object, the slab allocator puts it into a processor
+      private <indexterm>
+          <primary>slab allocator</primary>
+          <secondary>magazine</secondary>
-      private magazine cache, from where it can be precedently allocated
+        </indexterm>magazine cache, from where it can be precedently allocated
       again. Note that allocations satisfied from a magazine are already
       initialized by the constructor. When both of the processor cached
       magazines get full, the allocator will move one of the magazines to the
       list of full magazines. Similarily, when allocating from an empty
       processor magazine cache, the kernel will reload only one magazine from
       <para>Should HelenOS run short of memory, it would start deallocating
       objects from magazines, calling slab cache destructor on them and
       putting them back into slabs. When a slab contanins no allocated object,
       it is immediately freed.</para>
+      <para>
-      <para><figure>
+        <figure>
           <mediaobject id="slab_alloc">
             <imageobject role="html">
               <imagedata fileref="images/slab_alloc.png" format="PNG" />
             </imageobject>
           </mediaobject>
           <title>Slab allocator scheme.</title>
-        </figure></para>
+        </figure>
+      </para>
       <section>
         <title>Implementation</title>
         <para>The slab allocator is closely modelled after OpenSolaris slab
-        allocator by Jeff Bonwick and Jonathan Adams with the following
+        allocator by Jeff Bonwick and Jonathan Adams <xref
-        exceptions:<itemizedlist>
+        linkend="Bonwick01" /> with the following exceptions:<itemizedlist>
-            <listitem>
-               empty slabs are immediately deallocated and
+            <listitem>empty slabs are immediately deallocated and</listitem>
-            </listitem>
             <listitem>
               <para>empty magazines are deallocated when not needed.</para>
             </listitem>
           </itemizedlist>The following features are not currently supported
         but would be easy to do: <itemizedlist>
-            <listitem>
-               cache coloring and
+            <listitem>cache coloring and</listitem>
-            </listitem>
-            <listitem>
+            <listitem>dynamic magazine grow (different magazine sizes are
-               dynamic magazine grow (different magazine sizes are already supported, but the allocation strategy would need to be adjusted).
+            already supported, but the allocation strategy would need to be
-            </listitem>
+            adjusted).</listitem>
           </itemizedlist></para>
         <section>
           <title>Allocation/deallocation</title>
              Allowing, in general, to load and execute two programs that are linked on the same address without complicated relocations.
           </listitem>
         </itemizedlist></para>
       <para><!--
-                TLB shootdown ASID/ASID:PAGE/ALL.
-                TLB shootdown requests can come in asynchroniously
-                so there is a cache of TLB shootdown requests. Upon cache overflow TLB shootdown ALL is executed
                 <para>
                         Address spaces. Address space area (B+ tree). Only for uspace. Set of syscalls (shrink/extend etc).
                         Special address space area type - device - prohibits shrink/extend syscalls to call on it.
                         Address space has link to mapping tables (hierarchical - per Address space, hash - global tables).
                 </para>
 --></para>
     </section>
     <section>
-      <title>Paging</title>
-      <para>Virtual memory is usually using paged memory model, where virtual
-      memory address space is divided into the <emphasis>pages</emphasis>
-      (usually having size 4096 bytes) and physical memory is divided into the
-      frames (same sized as a page, of course). Each page may be mapped to
-      some frame and then, upon memory access to the virtual address, CPU
-      performs <emphasis>address translation</emphasis> during the instruction
-      execution. Non-existing mapping generates page fault exception, calling
-      kernel exception handler, thus allowing kernel to manipulate rules of
-      memory access. Information for pages mapping is stored by kernel in the
-      <link linkend="page_tables">page tables</link></para>
-      <para>The majority of the architectures use multi-level page tables,
-      which means need to access physical memory several times before getting
-      physical address. This fact would make serios performance overhead in
-      virtual memory management. To avoid this <link linkend="tlb">Traslation
-      Lookaside Buffer (TLB)</link> is used.</para>
-    </section>
-    <section>
       <title>Address spaces</title>
       <section>
+        <indexterm>
+          <primary>address space</primary>
+          <secondary>area</secondary>
+        </indexterm>
         <title>Address space areas</title>
         <para>Each address space consists of mutually disjunctive continuous
         address space areas. Address space area is precisely defined by its
         base address and the number of frames/pages is contains.</para>
         <para>Address space area , that define behaviour and permissions on
         the particular area. <itemizedlist>
-            <listitem>
-              <emphasis>AS_AREA_READ</emphasis>
+            <listitem><emphasis>AS_AREA_READ</emphasis> flag indicates reading
-               flag indicates reading permission.
-            </listitem>
-            <listitem>
-              <emphasis>AS_AREA_WRITE</emphasis>
-               flag indicates writing permission.
-            </listitem>
+            permission.</listitem>
-            <listitem>
-              <emphasis>AS_AREA_EXEC</emphasis>
+            <listitem><emphasis>AS_AREA_WRITE</emphasis> flag indicates
+            writing permission.</listitem>
+            <listitem><emphasis>AS_AREA_EXEC</emphasis> flag indicates code
-               flag indicates code execution permission. Some architectures do not support execution persmission restriction. In this case this flag has no effect.
+            execution permission. Some architectures do not support execution
-            </listitem>
+            persmission restriction. In this case this flag has no
-            <listitem>
+            effect.</listitem>
-              <emphasis>AS_AREA_DEVICE</emphasis>
+            <listitem><emphasis>AS_AREA_DEVICE</emphasis> marks area as mapped
-               marks area as mapped to the device memory.
-            </listitem>
+            to the device memory.</listitem>
           </itemizedlist></para>
         <para>Kernel provides possibility tasks create/expand/shrink/share its
         address space via the set of syscalls.</para>
       </section>
       <section>
+        <indexterm>
+          <primary>address space</primary>
+          <secondary>ASID</secondary>
+        </indexterm>
         <title>Address Space ID (ASID)</title>
         <para>When switching to the different task, kernel also require to
         switch mappings to the different address space. In case TLB cannot
         distinguish address space mappings, all mapping information in TLB
         impossible to use it as unique address space identifier for all tasks
         running in the system. In such situations special ASID stealing
         algoritm is used, which takes ASID from inactive task and assigns it
         to the active task.</para>
+        <indexterm>
+          <primary>address space</primary>
+          <secondary>ASID stealing</secondary>
+        </indexterm>
+        <para>
-        <para><classname>ASID stealing algoritm here.</classname></para>
+          <classname>ASID stealing algoritm here.</classname>
+        </para>
       </section>
     </section>
-    <section>
+    <section id="paging">
       <title>Virtual address translation</title>
-      <section id="page_tables">
+      <section>
-        <title>Page tables</title>
+        <title>Introduction</title>
+        <para>Virtual memory is usually using paged memory model, where
+        virtual memory address space is divided into the
+        <emphasis>pages</emphasis> (usually having size 4096 bytes) and
+        physical memory is divided into the frames (same sized as a page, of
+        course). Each page may be mapped to some frame and then, upon memory
+        access to the virtual address, CPU performs <emphasis>address
+        translation</emphasis> during the instruction execution. Non-existing
+        mapping generates page fault exception, calling kernel exception
+        handler, thus allowing kernel to manipulate rules of memory access.
+        Information for pages mapping is stored by kernel in the <link
+        linkend="page_tables">page tables</link></para>
+        <indexterm>
+          <primary>page tables</primary>
+        </indexterm>
+        <para>The majority of the architectures use multi-level page tables,
+        which means need to access physical memory several times before
+        getting physical address. This fact would make serios performance
+        overhead in virtual memory management. To avoid this <link
+        linkend="tlb">Traslation Lookaside Buffer (TLB)</link> is used.</para>
         <para>HelenOS kernel has two different approaches to the paging
         implementation: <emphasis>4 level page tables</emphasis> and
-        <emphasis>global hash tables</emphasis>, which are accessible via
+        <emphasis>global hash table</emphasis>, which are accessible via
         generic paging abstraction layer. Such different functionality was
         caused by the major architectural differences between supported
         platforms. This abstraction is implemented with help of the global
         structure of pointers to basic mapping functions
         <emphasis>page_mapping_operations</emphasis>. To achieve different
         functionality of page tables, corresponding layer must implement
         functions, declared in
         <emphasis>page_mapping_operations</emphasis></para>
+        <para>Thanks to the abstract paging interface, there was a place left
+        for more paging implementations (besides already implemented
+        hieararchical page tables and hash table), for example B-Tree based
-        <formalpara>
+        page tables.</para>
-          <title>4-level page tables</title>
+      </section>
-          <para>4-level page tables are the generalization of the hardware
-          capabilities of several architectures.<itemizedlist>
-              <listitem>
-                 ia32 uses 2-level page tables, with full hardware support.
-              </listitem>
+      <section id="page_tables">
-              <listitem>
-                 amd64 uses 4-level page tables, also coming with full hardware support.
-              </listitem>
-              <listitem>
+        <indexterm>
-                 mips and ppc32 have 2-level tables, software simulated support.
-              </listitem>
-            </itemizedlist></para>
+          <primary>page tables</primary>
-        </formalpara>
-        <formalpara>
+          <secondary>hierarchical</secondary>
-          <title>Global hash tables</title>
+        </indexterm>
+        <title>Hierarchical 4-level page tables</title>
-          <para>- global page hash table: existuje jen jedna v celem systemu
+        <para>Hierarchical 4-level page tables are the generalization of the
-          (vyuziva ji ia64), pozn. ia64 ma zatim vypnuty VHPT. Pouziva se
+        hardware capabilities of most architectures. Each address space has
-          genericke hash table s oddelenymi collision chains. ASID support is
+        its own page tables.<itemizedlist>
-          required to use global hash tables.</para>
+            <listitem>ia32 uses 2-level page tables, with full hardware
-        </formalpara>
+            support.</listitem>
+            <listitem>amd64 uses 4-level page tables, also coming with full
+            hardware support.</listitem>
-        <para>Thanks to the abstract paging interface, there is possibility
+            <listitem>mips and ppc32 have 2-level tables, software simulated
-        left have more paging implementations, for example B-Tree page
+            support.</listitem>
-        tables.</para>
+          </itemizedlist></para>
       </section>
-      <section id="tlb">
+      <section>
+        <indexterm>
-        <title>Translation Lookaside buffer</title>
+          <primary>page tables</primary>
-        <para>Due to the extensive overhead during the page mapping lookup in
-        the page tables, all architectures has fast assotiative cache memory
-        built-in CPU. This memory called TLB stores recently used page table
+          <secondary>hashing</secondary>
-        entries.</para>
+        </indexterm>
-        <section id="tlb_shootdown">
+        <title>Global hash table</title>
-          <title>TLB consistency. TLB shootdown algorithm.</title>
-          <para>Operating system is responsible for keeping TLB consistent by
+        <para>Implementation of the global hash table was encouraged by the
-          invalidating the contents of TLB, whenever there is some change in
+        ia64 architecture support. One of the major differences between global
-          page tables. Those changes may occur when page or group of pages
+        hash table and hierarchical tables is that global hash table exists
-          were unmapped, mapping is changed or system switching active address
-          space to schedule a new system task (which is a batch unmap of all
-          address space mappings). Moreover, this invalidation operation must
-          be done an all system CPUs because each CPU has its own independent
+        only once in the system and the hierarchical tables are maintained per
-          TLB cache. Thus maintaining TLB consistency on SMP configuration as
-          not as trivial task as it looks at the first glance. Naive solution
-          would assume remote TLB invalidatation, which is not possible on the
-          most of the architectures, because of the simple fact - flushing TLB
-          is allowed only on the local CPU and there is no possibility to
-          access other CPUs' TLB caches.</para>
+        address space.</para>
-          <para>Technique of remote invalidation of TLB entries is called "TLB
+        <para>Thus, hash table contains information about all address spaces
-          shootdown". HelenOS uses a variation of the algorithm described by
+        mappings in the system, so, the hash of an entry must contain
-          D. Black et al., "Translation Lookaside Buffer Consistency: A
-          Software Approach," Proc. Third Int'l Conf. Architectural Support
-          for Programming Languages and Operating Systems, 1989, pp.
+        information of both address space pointer or id and the virtual
--122.</para>
-          <para>As the situation demands, you will want partitial invalidation
-          of TLB caches. In case of simple memory mapping change it is
+        address of the page. Generic hash table implementation assumes that
-          necessary to invalidate only one or more adjacent pages. In case if
+        the addresses of the pointers to the address spaces are likely to be
-          the architecture is aware of ASIDs, during the address space
+        on the close addresses, so it uses least significant bits for hash;
-          switching, kernel invalidates only entries from this particular
+        also it assumes that the virtual page addresses have roughly the same
-          address space. Final option of the TLB invalidation is the complete
+        probability of occurring, so the least significant bits of VPN compose
-          TLB cache invalidation, which is the operation that flushes all
-          entries in TLB.</para>
+        the hash index.</para>
-          <para>TLB shootdown is performed in two phases. First, the initiator
+        <para>- global page hash table: existuje jen jedna v celem systemu
-          process sends an IPI message indicating the TLB shootdown request to
+        (vyuziva ji ia64), pozn. ia64 ma zatim vypnuty VHPT. Pouziva se
-          the rest of the CPUs. Then, it waits until all CPUs confirm TLB
+        genericke hash table s oddelenymi collision chains. ASID support is
-          invalidating action execution.</para>
+        required to use global hash tables.</para>
-        </section>
       </section>
     </section>
-    <section>
+    <section id="tlb">
+      <indexterm>
+        <primary>TLB</primary>
-      <title>---</title>
+      </indexterm>
+      <title>Translation Lookaside buffer</title>
+      <para>Due to the extensive overhead during the page mapping lookup in
+      the page tables, all architectures has fast assotiative cache memory
+      built-in CPU. This memory called TLB stores recently used page table
+      entries.</para>
+      <section id="tlb_shootdown">
+        <indexterm>
+          <primary>TLB</primary>
+          <secondary>TLB shootdown</secondary>
+        </indexterm>
+        <title>TLB consistency. TLB shootdown algorithm.</title>
+        <para>Operating system is responsible for keeping TLB consistent by
+        invalidating the contents of TLB, whenever there is some change in
+        page tables. Those changes may occur when page or group of pages were
+        unmapped, mapping is changed or system switching active address space
+        to schedule a new system task. Moreover, this invalidation operation
+        must be done an all system CPUs because each CPU has its own
+        independent TLB cache. Thus maintaining TLB consistency on SMP
+        configuration as not as trivial task as it looks on the first glance.
+        Naive solution would assume that is the CPU which wants to invalidate
+        TLB will invalidate TLB caches on other CPUs. It is not possible on
+        the most of the architectures, because of the simple fact - flushing
+        TLB is allowed only on the local CPU and there is no possibility to
+        access other CPUs' TLB caches, thus invalidate TLB remotely.</para>
+        <para>Technique of remote invalidation of TLB entries is called "TLB
+        shootdown". HelenOS uses a variation of the algorithm described by D.
+        Black et al., "Translation Lookaside Buffer Consistency: A Software
+        Approach," Proc. Third Int'l Conf. Architectural Support for
+        Programming Languages and Operating Systems, 1989, pp. 113-122. <xref
+        linkend="Black89" /></para>
+        <para>As the situation demands, you will want partitial invalidation
+        of TLB caches. In case of simple memory mapping change it is necessary
+        to invalidate only one or more adjacent pages. In case if the
+        architecture is aware of ASIDs, when kernel needs to dump some ASID to
+        use by another task, it invalidates only entries from this particular
+        address space. Final option of the TLB invalidation is the complete
+        TLB cache invalidation, which is the operation that flushes all
+        entries in TLB.</para>
-      <para>At the moment HelenOS does not support swapping.</para>
+        <para>TLB shootdown is performed in two phases.</para>
+        <formalpara>
+          <title>Phase 1.</title>
-      <para>- pouzivame vypadky stranky k alokaci ramcu on-demand v ramci
+          <para>First, initiator locks a global TLB spinlock, then request is
+          being put to the local request cache of every other CPU in the
+          system protected by its spinlock. In case the cache is full, all
-      as_area - na architekturach, ktere to podporuji, podporujeme non-exec
+          requests in the cache are replaced by one request, indicating global
+          TLB flush. Then the initiator thread sends an IPI message indicating
+          the TLB shootdown request to the rest of the CPUs and waits actively
+          until all CPUs confirm TLB invalidating action execution by setting
+          up a special flag. After setting this flag this thread is blocked on
+          the TLB spinlock, held by the initiator.</para>
+        </formalpara>
+        <formalpara>
+          <title>Phase 2.</title>
+          <para>All CPUs are waiting on the TLB spinlock to execute TLB
+          invalidation action and have indicated their intention to the
+          initiator. Initiator continues, cleaning up its TLB and releasing
+          the global TLB spinlock. After this all other CPUs gain and
+          immidiately release TLB spinlock and perform TLB invalidation
-      stranky</para>
+          actions.</para>
+        </formalpara>
+      </section>
     </section>
   </section>
 </chapter>

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