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Line 39... Line 39...
39
#include <arch/asm.h>
39
#include <arch/asm.h>
40
#include <mm/slab.h>
40
#include <mm/slab.h>
41
#include <ddi/device.h>
41
#include <ddi/device.h>
42
#include <synch/spinlock.h>
42
#include <synch/spinlock.h>
43
 
43
 
-
 
44
static irq_ownership_t cuda_claim(irq_t *irq);
44
static void cuda_packet_handle(cuda_instance_t *instance, uint8_t *buf, size_t len);
45
static void cuda_irq_handler(irq_t *irq);
-
 
46
 
45
static void cuda_irq_listen(irq_t *irq);
47
static void cuda_irq_listen(irq_t *irq);
46
static void cuda_irq_receive(irq_t *irq);
48
static void cuda_irq_receive(irq_t *irq);
47
static void cuda_irq_rcv_end(irq_t *irq, void *buf, size_t *len);
49
static void cuda_irq_rcv_end(irq_t *irq, void *buf, size_t *len);
-
 
50
static void cuda_irq_send_start(irq_t *irq);
-
 
51
static void cuda_irq_send(irq_t *irq);
-
 
52
 
-
 
53
static void cuda_packet_handle(cuda_instance_t *instance, uint8_t *buf, size_t len);
-
 
54
static void cuda_send_start(cuda_instance_t *instance);
-
 
55
static void cuda_autopoll_set(cuda_instance_t *instance, bool enable);
48
 
56
 
49
/** B register fields */
57
/** B register fields */
50
enum {
58
enum {
51
    TREQ    = 0x08,
59
    TREQ    = 0x08,
52
    TACK    = 0x10,
60
    TACK    = 0x10,
Line 65... Line 73...
65
/** ACR register fields */
73
/** ACR register fields */
66
enum {
74
enum {
67
    SR_OUT  = 0x10
75
    SR_OUT  = 0x10
68
};
76
};
69
 
77
 
-
 
78
/** Packet types */
-
 
79
enum {
-
 
80
    PT_ADB  = 0x00,
-
 
81
    PT_CUDA = 0x01
-
 
82
};
-
 
83
 
-
 
84
/** CUDA packet types */
-
 
85
enum {
-
 
86
    CPT_AUTOPOLL    = 0x01
-
 
87
};
-
 
88
 
-
 
89
cuda_instance_t *cuda_init(cuda_t *dev, inr_t inr, cir_t cir, void *cir_arg)
-
 
90
{
-
 
91
    cuda_instance_t *instance
-
 
92
        = malloc(sizeof(cuda_instance_t), FRAME_ATOMIC);
-
 
93
    if (instance) {
-
 
94
        instance->cuda = dev;
-
 
95
        instance->kbrdin = NULL;
-
 
96
        instance->xstate = cx_listen;
-
 
97
        instance->bidx = 0;
-
 
98
        instance->snd_bytes = 0;
-
 
99
 
-
 
100
        spinlock_initialize(&instance->dev_lock, "cuda_dev");
-
 
101
 
-
 
102
        /* Disable all interrupts from CUDA. */
-
 
103
        pio_write_8(&dev->ier, IER_CLR | ALL_INT);
-
 
104
 
-
 
105
        irq_initialize(&instance->irq);
-
 
106
        instance->irq.devno = device_assign_devno();
-
 
107
        instance->irq.inr = inr;
-
 
108
        instance->irq.claim = cuda_claim;
-
 
109
        instance->irq.handler = cuda_irq_handler;
-
 
110
        instance->irq.instance = instance;
-
 
111
        instance->irq.cir = cir;
-
 
112
        instance->irq.cir_arg = cir_arg;
-
 
113
        instance->irq.preack = true;
-
 
114
    }
-
 
115
   
-
 
116
    return instance;
-
 
117
}
-
 
118
 
70
#include <print.h>
119
#include <print.h>
-
 
120
void cuda_wire(cuda_instance_t *instance, indev_t *kbrdin)
-
 
121
{
-
 
122
    cuda_t *dev = instance->cuda;
-
 
123
 
-
 
124
    ASSERT(instance);
-
 
125
    ASSERT(kbrdin);
-
 
126
 
-
 
127
    instance->kbrdin = kbrdin;
-
 
128
    irq_register(&instance->irq);
-
 
129
 
-
 
130
    /* Enable SR interrupt. */
-
 
131
    pio_write_8(&dev->ier, TIP | TREQ);
-
 
132
    pio_write_8(&dev->ier, IER_SET | SR_INT);
-
 
133
 
-
 
134
    /* Enable ADB autopolling. */
-
 
135
    cuda_autopoll_set(instance, true);
-
 
136
}
-
 
137
 
71
static irq_ownership_t cuda_claim(irq_t *irq)
138
static irq_ownership_t cuda_claim(irq_t *irq)
72
{
139
{
73
    cuda_instance_t *instance = irq->instance;
140
    cuda_instance_t *instance = irq->instance;
74
    cuda_t *dev = instance->cuda;
141
    cuda_t *dev = instance->cuda;
75
    uint8_t ifr;
142
    uint8_t ifr;
76
 
143
 
-
 
144
    spinlock_lock(&instance->dev_lock);
77
    ifr = pio_read_8(&dev->ifr);
145
    ifr = pio_read_8(&dev->ifr);
-
 
146
    spinlock_unlock(&instance->dev_lock);
78
 
147
 
79
    if ((ifr & SR_INT) == 0)
148
    if ((ifr & SR_INT) == 0)
80
        return IRQ_DECLINE;
149
        return IRQ_DECLINE;
81
 
150
 
82
    return IRQ_ACCEPT;
151
    return IRQ_ACCEPT;
Line 100... Line 169...
100
    switch (instance->xstate) {
169
    switch (instance->xstate) {
101
    case cx_listen: cuda_irq_listen(irq); break;
170
    case cx_listen: cuda_irq_listen(irq); break;
102
    case cx_receive: cuda_irq_receive(irq); break;
171
    case cx_receive: cuda_irq_receive(irq); break;
103
    case cx_rcv_end: cuda_irq_rcv_end(irq, rbuf, &len);
172
    case cx_rcv_end: cuda_irq_rcv_end(irq, rbuf, &len);
104
        handle = true; break;
173
        handle = true; break;
-
 
174
    case cx_send_start: cuda_irq_send_start(irq); break;
-
 
175
    case cx_send: cuda_irq_send(irq); break;
105
    }
176
    }
106
 
177
 
107
    spinlock_unlock(&instance->dev_lock);
178
    spinlock_unlock(&instance->dev_lock);
108
 
179
 
109
    /* Handle an incoming packet. */
180
    /* Handle an incoming packet. */
Line 169... Line 240...
169
    uint8_t data, b;
240
    uint8_t data, b;
170
 
241
 
171
    b = pio_read_8(&dev->b);
242
    b = pio_read_8(&dev->b);
172
    data = pio_read_8(&dev->sr);
243
    data = pio_read_8(&dev->sr);
173
 
244
 
174
    instance->xstate = cx_listen;
-
 
175
 
-
 
176
    if ((b & TREQ) == 0) {
245
    if ((b & TREQ) == 0) {
177
        instance->xstate = cx_receive;
246
        instance->xstate = cx_receive;
178
        pio_write_8(&dev->b, b & ~TIP);
247
        pio_write_8(&dev->b, b & ~TIP);
179
    } else {
248
    } else {
180
        instance->xstate = cx_listen;
249
        instance->xstate = cx_listen;
-
 
250
        cuda_send_start(instance);
181
    }
251
    }
182
 
252
 
183
        memcpy(buf, instance->rcv_buf, instance->bidx);
253
        memcpy(buf, instance->rcv_buf, instance->bidx);
184
        *len = instance->bidx;
254
        *len = instance->bidx;
185
    instance->bidx = 0;
255
    instance->bidx = 0;
186
}
256
}
187
 
257
 
-
 
258
/** Interrupt in send_start state.
-
 
259
 *
-
 
260
 * Process result of sending first byte (and send second on success).
-
 
261
 */
-
 
262
static void cuda_irq_send_start(irq_t *irq)
-
 
263
{
-
 
264
    cuda_instance_t *instance = irq->instance;
-
 
265
    cuda_t *dev = instance->cuda;
-
 
266
    uint8_t b;
-
 
267
 
-
 
268
    b = pio_read_8(&dev->b);
-
 
269
 
-
 
270
    if ((b & TREQ) == 0) {
-
 
271
        /* Collision */
-
 
272
        pio_write_8(&dev->acr, pio_read_8(&dev->acr) & ~SR_OUT);
-
 
273
        pio_read_8(&dev->sr);
-
 
274
        pio_write_8(&dev->b, pio_read_8(&dev->b) | TIP | TACK);
-
 
275
        instance->xstate = cx_listen;
-
 
276
        return;
-
 
277
    }
-
 
278
 
-
 
279
    pio_write_8(&dev->sr, instance->snd_buf[1]);
-
 
280
    pio_write_8(&dev->b, pio_read_8(&dev->b) ^ TACK);
-
 
281
    instance->bidx = 2;
-
 
282
 
-
 
283
    instance->xstate = cx_send;
-
 
284
}
-
 
285
 
-
 
286
/** Interrupt in send state.
-
 
287
 *
-
 
288
 * Send next byte or terminate transmission.
-
 
289
 */
-
 
290
static void cuda_irq_send(irq_t *irq)
-
 
291
{
-
 
292
    cuda_instance_t *instance = irq->instance;
-
 
293
    cuda_t *dev = instance->cuda;
-
 
294
 
-
 
295
    if (instance->bidx < instance->snd_bytes) {
-
 
296
        /* Send next byte. */
-
 
297
        pio_write_8(&dev->sr, instance->snd_buf[instance->bidx++]);
-
 
298
        pio_write_8(&dev->b, pio_read_8(&dev->b) ^ TACK);
-
 
299
        return;
-
 
300
    }
-
 
301
 
-
 
302
    /* End transfer. */
-
 
303
    instance->snd_bytes = 0;
-
 
304
    instance->bidx = 0;
-
 
305
 
-
 
306
    pio_write_8(&dev->acr, pio_read_8(&dev->acr) & ~SR_OUT);
-
 
307
    pio_read_8(&dev->sr);
-
 
308
    pio_write_8(&dev->b, pio_read_8(&dev->b) | TACK | TIP);
-
 
309
 
-
 
310
    instance->xstate = cx_listen;
-
 
311
    /* TODO: Match reply with request. */
-
 
312
}
-
 
313
 
188
static void cuda_packet_handle(cuda_instance_t *instance, uint8_t *data, size_t len)
314
static void cuda_packet_handle(cuda_instance_t *instance, uint8_t *data, size_t len)
189
{
315
{
190
    if (data[0] != 0x00 || data[1] != 0x40 || (data[2] != 0x2c
316
    if (data[0] != 0x00 || data[1] != 0x40 || (data[2] != 0x2c
191
        && data[2] != 0x8c))
317
        && data[2] != 0x8c))
192
        return;
318
        return;
Line 196... Line 322...
196
        indev_push_character(instance->kbrdin, data[3]);       
322
        indev_push_character(instance->kbrdin, data[3]);       
197
    if (data[4] != 0xff)
323
    if (data[4] != 0xff)
198
        indev_push_character(instance->kbrdin, data[4]);
324
        indev_push_character(instance->kbrdin, data[4]);
199
}
325
}
200
 
326
 
201
cuda_instance_t *cuda_init(cuda_t *dev, inr_t inr, cir_t cir, void *cir_arg)
327
static void cuda_autopoll_set(cuda_instance_t *instance, bool enable)
202
{
328
{
203
    cuda_instance_t *instance
329
    instance->snd_buf[0] = PT_CUDA;
204
        = malloc(sizeof(cuda_instance_t), FRAME_ATOMIC);
-
 
205
    if (instance) {
-
 
206
        instance->cuda = dev;
330
    instance->snd_buf[1] = CPT_AUTOPOLL;
207
        instance->kbrdin = NULL;
331
    instance->snd_buf[2] = enable ? 0x01 : 0x00;
208
        instance->xstate = cx_listen;
332
    instance->snd_bytes = 3;
209
        instance->bidx = 0;
333
    instance->bidx = 0;
210
 
-
 
211
        spinlock_initialize(&instance->dev_lock, "cuda_dev");
-
 
212
 
-
 
213
        /* Disable all interrupts from CUDA. */
-
 
214
        pio_write_8(&dev->ier, IER_CLR | ALL_INT);
-
 
215
 
334
 
216
        irq_initialize(&instance->irq);
-
 
217
        instance->irq.devno = device_assign_devno();
-
 
218
        instance->irq.inr = inr;
-
 
219
        instance->irq.claim = cuda_claim;
-
 
220
        instance->irq.handler = cuda_irq_handler;
-
 
221
        instance->irq.instance = instance;
-
 
222
        instance->irq.cir = cir;
-
 
223
        instance->irq.cir_arg = cir_arg;
-
 
224
        instance->irq.preack = true;
-
 
225
    }
-
 
226
   
-
 
227
    return instance;
335
    cuda_send_start(instance);
228
}
336
}
229
 
337
 
230
void cuda_wire(cuda_instance_t *instance, indev_t *kbrdin)
338
static void cuda_send_start(cuda_instance_t *instance)
231
{
339
{
232
    cuda_t *dev = instance->cuda;
340
    cuda_t *dev = instance->cuda;
233
 
341
 
234
    ASSERT(instance);
342
    ASSERT(instance->xstate == cx_listen);
235
    ASSERT(kbrdin);
-
 
236
 
343
 
237
    instance->kbrdin = kbrdin;
344
    if (instance->snd_bytes == 0)
238
    irq_register(&instance->irq);
345
        return;
239
 
346
 
240
    /* Enable SR interrupt. */
347
    /* Check for incoming data. */
241
    pio_write_8(&dev->ier, TIP | TREQ);
348
    if ((pio_read_8(&dev->b) & TREQ) == 0)
-
 
349
        return;
-
 
350
 
-
 
351
    pio_write_8(&dev->acr, pio_read_8(&dev->acr) | SR_OUT);
242
    pio_write_8(&dev->ier, IER_SET | SR_INT);
352
    pio_write_8(&dev->sr, instance->snd_buf[0]);
-
 
353
    pio_write_8(&dev->b, pio_read_8(&dev->b) & ~TIP);
-
 
354
 
-
 
355
    instance->xstate = cx_send_start;
243
}
356
}
244
 
357
 
-
 
358
 
245
/** @}
359
/** @}
246
 */
360
 */