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Rev 1816 Rev 1829
Line 73... Line 73...
73 
    { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
 73 
    { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
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    /* TLS descriptor */
 74 
    /* TLS descriptor */
75 
    { 0xffff, 0, 0, AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_USER, 0xf, 0, 0, 1, 1, 0 },
 75 
    { 0xffff, 0, 0, AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_USER, 0xf, 0, 0, 1, 1, 0 },
76 
};
 76 
};
77 
 
 77 
 
78 
static idescriptor_t idt[IDT_ITEMS];
 78 
static trap_info_t traps[IDT_ITEMS + 1];
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 79 
 
80 
static tss_t tss;
 80 
static tss_t tss;
81 
 
 81 
 
82 
tss_t *tss_p = NULL;
 82 
tss_t *tss_p = NULL;
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 83 
 
Line 96... Line 96...
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{
 96 
{
97 
    d->limit_0_15 = limit & 0xffff;
 97 
    d->limit_0_15 = limit & 0xffff;
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    d->limit_16_19 = (limit >> 16) & 0xf;
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    d->limit_16_19 = (limit >> 16) & 0xf;
99 
}
 99 
}
100 
 
 100 
 
101 
void idt_setoffset(idescriptor_t *d, uintptr_t offset)
 - 
 
102 
{
 - 
 
103 
    /*
 - 
 
104 
     * Offset is a linear address.
 - 
 
105 
     */
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106 
    d->offset_0_15 = offset & 0xffff;
 - 
 
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    d->offset_16_31 = offset >> 16;
 - 
 
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}
 - 
 
109 
 
 - 
 
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void tss_initialize(tss_t *t)
 101 
void tss_initialize(tss_t *t)
111 
{
 102 
{
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    memsetb((uintptr_t) t, sizeof(struct tss), 0);
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    memsetb((uintptr_t) t, sizeof(struct tss), 0);
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}
 104 
}
114 
 
 105 
 
115 
/*
 - 
 
116 
 * This function takes care of proper setup of IDT and IDTR.
 - 
 
117 
 */
 - 
 
118 
void idt_init(void)
 106 
void traps_init(void)
119 
{
 107 
{
120 
    idescriptor_t *d;
 - 
 
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    int i;
 108 
    index_t i;
122 
 
 109 
   
123 
    for (i = 0; i < IDT_ITEMS; i++) {
 110 
    for (i = 0; i < IDT_ITEMS; i++) {
124 
        d = &idt[i];
 - 
 
125 
 
 - 
 
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        d->unused = 0;
 111 
        traps[i].vector = i;
127 
        d->selector = selector(KTEXT_DES);
 - 
 
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 112 
       
129 
        d->access = AR_PRESENT | AR_INTERRUPT;  /* masking interrupt */
 - 
 
130 
 
 - 
 
131 
        if (i == VECTOR_SYSCALL) {
 113 
        if (i == VECTOR_SYSCALL)
132 
            /*
 - 
 
133 
             * The syscall interrupt gate must be calleable from userland.
 114 
            traps[i].flags = 3;
134 
             */
 115 
        else
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            d->access |= DPL_USER;
 116 
            traps[i].flags = 0;
136 
        }
 - 
 
137 
       
 117 
       
- 
 
 118 
        traps[i].cs = XEN_CS;
138 
        idt_setoffset(d, ((uintptr_t) interrupt_handlers) + i*interrupt_handler_size);
 119 
        traps[i].address = ((uintptr_t) interrupt_handlers) + i * interrupt_handler_size;
139 
        exc_register(i, "undef", (iroutine) null_interrupt);
 120 
        exc_register(i, "undef", (iroutine) null_interrupt);
140 
    }
 121 
    }
- 
 
 122 
    traps[IDT_ITEMS].vector = 0;
- 
 
 123 
    traps[IDT_ITEMS].flags = 0;
- 
 
 124 
    traps[IDT_ITEMS].cs = 0;
- 
 
 125 
    traps[IDT_ITEMS].address = NULL;
- 
 
 126 
   
141 
    exc_register(13, "gp_fault", (iroutine) gp_fault);
 127 
    exc_register(13, "gp_fault", (iroutine) gp_fault);
142 
    exc_register( 7, "nm_fault", (iroutine) nm_fault);
 128 
    exc_register( 7, "nm_fault", (iroutine) nm_fault);
143 
    exc_register(12, "ss_fault", (iroutine) ss_fault);
 129 
    exc_register(12, "ss_fault", (iroutine) ss_fault);
144 
    exc_register(19, "simd_fp", (iroutine) simd_fp_exception);
 130 
    exc_register(19, "simd_fp", (iroutine) simd_fp_exception);
145 
}
 131 
}
Line 170... Line 156...
170 
}
 156 
}
171 
 
 157 
 
172 
void pm_init(void)
 158 
void pm_init(void)
173 
{
 159 
{
174 
    descriptor_t *gdt_p = (descriptor_t *) gdtr.base;
 160 
    descriptor_t *gdt_p = (descriptor_t *) gdtr.base;
175 
    ptr_16_32_t idtr;
 - 
 
176 
 
 161 
 
177 
    /*
 - 
 
178 
     * Update addresses in GDT and IDT to their virtual counterparts.
 - 
 
179 
     */
 - 
 
180 
    idtr.limit = sizeof(idt);
 - 
 
181 
    idtr.base = (uintptr_t) idt;
 - 
 
182 
//  gdtr_load(&gdtr);
 162 
//  gdtr_load(&gdtr);
183 
//  idtr_load(&idtr);
 - 
 
184 
   
 163 
   
185 
    /*
 - 
 
186 
     * Each CPU has its private GDT and TSS.
 - 
 
187 
     * All CPUs share one IDT.
 - 
 
188 
     */
 - 
 
189 
 
 - 
 
190 
//  if (config.cpu_active == 1) {
 164 
    if (config.cpu_active == 1) {
191 
//      idt_init();
 165 
        traps_init();
- 
 
 166 
        xen_set_trap_table(traps);
192 
//      /*
 167 
        /*
193 
//       * NOTE: bootstrap CPU has statically allocated TSS, because
 168 
         * NOTE: bootstrap CPU has statically allocated TSS, because
194 
//       * the heap hasn't been initialized so far.
 169 
         * the heap hasn't been initialized so far.
195 
//       */
 170 
         */
196 
        tss_p = &tss;
 171 
        tss_p = &tss;
197 
//  }
 - 
 
198 
//  else {
 172 
    } else {
199 
//      tss_p = (tss_t *) malloc(sizeof(tss_t), FRAME_ATOMIC);
 173 
        tss_p = (tss_t *) malloc(sizeof(tss_t), FRAME_ATOMIC);
200 
//      if (!tss_p)
 174 
        if (!tss_p)
201 
//          panic("could not allocate TSS\n");
 175 
            panic("could not allocate TSS\n");
202 
//  }
 176 
    }
203 
 
 177 
 
204 
//  tss_initialize(tss_p);
 178 
//  tss_initialize(tss_p);
205 
   
 179 
   
206 
    gdt_p[TSS_DES].access = AR_PRESENT | AR_TSS | DPL_KERNEL;
 180 
    gdt_p[TSS_DES].access = AR_PRESENT | AR_TSS | DPL_KERNEL;
207 
    gdt_p[TSS_DES].special = 1;
 181 
    gdt_p[TSS_DES].special = 1;