Subversion Repositories HelenOS

Rev

Rev 1810 | Go to most recent revision | Show entire file | Ignore whitespace | Details | Blame | Last modification | View Log | RSS feed

Rev 1810 Rev 1816
Line 71... Line 71...
71 
    { 0xffff, 0, 0, AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_USER, 0xf, 0, 0, 1, 1, 0 },
 71 
    { 0xffff, 0, 0, AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_USER, 0xf, 0, 0, 1, 1, 0 },
72 
    /* TSS descriptor - set up will be completed later */
 72 
    /* TSS descriptor - set up will be completed later */
73 
    { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
 73 
    { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
74 
    /* TLS descriptor */
 74 
    /* TLS descriptor */
75 
    { 0xffff, 0, 0, AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_USER, 0xf, 0, 0, 1, 1, 0 },
 75 
    { 0xffff, 0, 0, AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_USER, 0xf, 0, 0, 1, 1, 0 },
76 
    /* VESA Init descriptor */
 - 
 
77 
#ifdef CONFIG_FB
 - 
 
78 
    { 0xffff, 0, VESA_INIT_SEGMENT>>12, AR_PRESENT | AR_CODE | DPL_KERNEL, 0xf, 0, 0, 0, 0, 0 }
 - 
 
79 
#endif 
- 
 
80 
};
 76 
};
81 
 
 77 
 
82 
static idescriptor_t idt[IDT_ITEMS];
 78 
static idescriptor_t idt[IDT_ITEMS];
83 
 
 79 
 
84 
static tss_t tss;
 80 
static tss_t tss;
Line 150... Line 146...
150 
 
 146 
 
151 
 
 147 
 
152 
/* Clean IOPL(12,13) and NT(14) flags in EFLAGS register */
 148 
/* Clean IOPL(12,13) and NT(14) flags in EFLAGS register */
153 
static void clean_IOPL_NT_flags(void)
 149 
static void clean_IOPL_NT_flags(void)
154 
{
 150 
{
155 
    __asm__ volatile (
 151 
//  __asm__ volatile (
156 
        "pushfl\n"
 152 
//      "pushfl\n"
157 
        "pop %%eax\n"
 153 
//      "pop %%eax\n"
158 
        "and $0xffff8fff, %%eax\n"
 154 
//      "and $0xffff8fff, %%eax\n"
159 
        "push %%eax\n"
 155 
//      "push %%eax\n"
160 
        "popfl\n"
 156 
//      "popfl\n"
161 
        : : : "eax"
 157 
//      : : : "eax"
162 
    );
 158 
//  );
163 
}
 159 
}
164 
 
 160 
 
165 
/* Clean AM(18) flag in CR0 register */
 161 
/* Clean AM(18) flag in CR0 register */
166 
static void clean_AM_flag(void)
 162 
static void clean_AM_flag(void)
167 
{
 163 
{
168 
    __asm__ volatile (
 164 
//  __asm__ volatile (
169 
        "mov %%cr0, %%eax\n"
 165 
//      "mov %%cr0, %%eax\n"
170 
        "and $0xfffbffff, %%eax\n"
 166 
//      "and $0xfffbffff, %%eax\n"
171 
        "mov %%eax, %%cr0\n"
 167 
//      "mov %%eax, %%cr0\n"
172 
        : : : "eax"
 168 
//      : : : "eax"
173 
    );
 169 
//  );
174 
}
 170 
}
175 
 
 171 
 
176 
void pm_init(void)
 172 
void pm_init(void)
177 
{
 173 
{
178 
    descriptor_t *gdt_p = (descriptor_t *) gdtr.base;
 174 
    descriptor_t *gdt_p = (descriptor_t *) gdtr.base;
Line 181... Line 177...
181 
    /*
 177 
    /*
182 
     * Update addresses in GDT and IDT to their virtual counterparts.
 178 
     * Update addresses in GDT and IDT to their virtual counterparts.
183 
     */
 179 
     */
184 
    idtr.limit = sizeof(idt);
 180 
    idtr.limit = sizeof(idt);
185 
    idtr.base = (uintptr_t) idt;
 181 
    idtr.base = (uintptr_t) idt;
186 
    gdtr_load(&gdtr);
 182 
//  gdtr_load(&gdtr);
187 
    idtr_load(&idtr);
 183 
//  idtr_load(&idtr);
188 
   
 184 
   
189 
    /*
 185 
    /*
190 
     * Each CPU has its private GDT and TSS.
 186 
     * Each CPU has its private GDT and TSS.
191 
     * All CPUs share one IDT.
 187 
     * All CPUs share one IDT.
192 
     */
 188 
     */
193 
 
 189 
 
194 
    if (config.cpu_active == 1) {
 190 
//  if (config.cpu_active == 1) {
195 
        idt_init();
 191 
//      idt_init();
196 
        /*
 192 
//      /*
197 
         * NOTE: bootstrap CPU has statically allocated TSS, because
 193 
//       * NOTE: bootstrap CPU has statically allocated TSS, because
198 
         * the heap hasn't been initialized so far.
 194 
//       * the heap hasn't been initialized so far.
199 
         */
 195 
//       */
200 
        tss_p = &tss;
 196 
        tss_p = &tss;
201 
    }
 197 
//  }
202 
    else {
 198 
//  else {
203 
        tss_p = (tss_t *) malloc(sizeof(tss_t), FRAME_ATOMIC);
 199 
//      tss_p = (tss_t *) malloc(sizeof(tss_t), FRAME_ATOMIC);
204 
        if (!tss_p)
 200 
//      if (!tss_p)
205 
            panic("could not allocate TSS\n");
 201 
//          panic("could not allocate TSS\n");
206 
    }
 202 
//  }
207 
 
 203 
 
208 
    tss_initialize(tss_p);
 204 
//  tss_initialize(tss_p);
209 
   
 205 
   
210 
    gdt_p[TSS_DES].access = AR_PRESENT | AR_TSS | DPL_KERNEL;
 206 
    gdt_p[TSS_DES].access = AR_PRESENT | AR_TSS | DPL_KERNEL;
211 
    gdt_p[TSS_DES].special = 1;
 207 
    gdt_p[TSS_DES].special = 1;
212 
    gdt_p[TSS_DES].granularity = 0;
 208 
    gdt_p[TSS_DES].granularity = 0;
213 
   
 209 
   
Line 216... Line 212...
216 
 
 212 
 
217 
    /*
 213 
    /*
218 
     * As of this moment, the current CPU has its own GDT pointing
 214 
     * As of this moment, the current CPU has its own GDT pointing
219 
     * to its own TSS. We just need to load the TR register.
 215 
     * to its own TSS. We just need to load the TR register.
220 
     */
 216 
     */
221 
    tr_load(selector(TSS_DES));
 217 
//  tr_load(selector(TSS_DES));
222 
   
 218 
   
223 
    clean_IOPL_NT_flags();    /* Disable I/O on nonprivileged levels and clear NT flag. */
 219 
    clean_IOPL_NT_flags();    /* Disable I/O on nonprivileged levels and clear NT flag. */
224 
    clean_AM_flag();          /* Disable alignment check */
 220 
    clean_AM_flag();          /* Disable alignment check */
225 
}
 221 
}
226 
 
 222