WebSVN – HelenOS – Diff – /trunk/kernel/arch/sparc64/src/smp/ipi.c


/*
 * Copyright (c) 2006 Jakub Jermar
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * - Redistributions of source code must retain the above copyright
 *   notice, this list of conditions and the following disclaimer.
 * - Redistributions in binary form must reproduce the above copyright
 *   notice, this list of conditions and the following disclaimer in the
 *   documentation and/or other materials provided with the distribution.
 * - The name of the author may not be used to endorse or promote products
 *   derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
/** @addtogroup sparc64
 * @{
 */
/** @file
 */
 
#include <smp/ipi.h>
#include <cpu.h>
#include <arch.h>
#include <arch/cpu.h>
#include <arch/asm.h>
#include <config.h>
#include <mm/tlb.h>
#include <arch/interrupt.h>
#include <arch/trap/interrupt.h>
#include <arch/barrier.h>
#include <preemption.h>
#include <time/delay.h>
#include <panic.h>
 
/** Set the contents of the outgoing interrupt vector data.
 *
 * The first data item (data 0) will be set to the value of func, the
 * rest of the vector will contain zeros.
 *
 * This is a helper function used from within the cross_call function.
 *
 * @param func value the first data item of the vector will be set to
 */
static inline void set_intr_w_data(void (* func)(void))
{
#if defined (US)
    asi_u64_write(ASI_INTR_W, ASI_UDB_INTR_W_DATA_0, (uintptr_t) func);
    asi_u64_write(ASI_INTR_W, ASI_UDB_INTR_W_DATA_1, 0);
    asi_u64_write(ASI_INTR_W, ASI_UDB_INTR_W_DATA_2, 0);
#elif defined (US3)
    asi_u64_write(ASI_INTR_W, VA_INTR_W_DATA_0, (uintptr_t) func);
    asi_u64_write(ASI_INTR_W, VA_INTR_W_DATA_1, 0);
    asi_u64_write(ASI_INTR_W, VA_INTR_W_DATA_2, 0);
    asi_u64_write(ASI_INTR_W, VA_INTR_W_DATA_3, 0);
    asi_u64_write(ASI_INTR_W, VA_INTR_W_DATA_4, 0);
    asi_u64_write(ASI_INTR_W, VA_INTR_W_DATA_5, 0);
    asi_u64_write(ASI_INTR_W, VA_INTR_W_DATA_6, 0);
    asi_u64_write(ASI_INTR_W, VA_INTR_W_DATA_7, 0);
#endif
}
 
/** Invoke function on another processor.
 *
 * Currently, only functions without arguments are supported.
 * Supporting more arguments in the future should be no big deal.
 *
 * Interrupts must be disabled prior to this call.
 *
 * @param mid MID of the target processor.
 * @param func Function to be invoked.
 */
static void cross_call(int mid, void (* func)(void))
{
    uint64_t status;
    bool done;
 
    /*
     * This function might enable interrupts for a while.
     * In order to prevent migration to another processor,
     * we explicitly disable preemption.
     */
   
    preemption_disable();
   
    status = asi_u64_read(ASI_INTR_DISPATCH_STATUS, 0);
    if (status & INTR_DISPATCH_STATUS_BUSY)
        panic("Interrupt Dispatch Status busy bit set.");
   
    ASSERT(!(pstate_read() & PSTATE_IE_BIT));
   
    do {
        set_intr_w_data(func);
        asi_u64_write(ASI_INTR_W,
            (mid << INTR_VEC_DISPATCH_MID_SHIFT) |
            VA_INTR_W_DISPATCH, 0);
   
        membar();
       
        do {
            status = asi_u64_read(ASI_INTR_DISPATCH_STATUS, 0);
        } while (status & INTR_DISPATCH_STATUS_BUSY);
       
        done = !(status & INTR_DISPATCH_STATUS_NACK);
        if (!done) {
            /*
             * Prevent deadlock.
             */        
            (void) interrupts_enable();
            delay(20 + (tick_read() & 0xff));
            (void) interrupts_disable();
        }
    } while (done);
   
    preemption_enable();
}
 
/*
 * Deliver IPI to all processors except the current one.
 *
 * The sparc64 architecture does not support any group addressing
 * which is found, for instance, on ia32 and amd64. Therefore we
 * need to simulate the broadcast by sending the message to
 * all target processors step by step.
 *
 * We assume that interrupts are disabled.
 *
 * @param ipi IPI number.
 */
void ipi_broadcast_arch(int ipi)
{
    unsigned int i;
   
    void (* func)(void);
   
    switch (ipi) {
    case IPI_TLB_SHOOTDOWN:
        func = tlb_shootdown_ipi_recv;
        break;
    default:
        panic("Unknown IPI (%d).", ipi);
        break;
    }
   
    /*
     * As long as we don't support hot-plugging
     * or hot-unplugging of CPUs, we can walk
     * the cpus array and read processor's MID
     * without locking.
     */
   
    for (i = 0; i < config.cpu_active; i++) {
        if (&cpus[i] == CPU)
            continue;       /* skip the current CPU */
 
        cross_call(cpus[i].arch.mid, func);
    }
}
 
/** @}
 */
 

Subversion Repositories HelenOS

(root)/trunk/kernel/arch/sparc64/src/smp/ipi.c – Rev 3672 → 3790

Rev 3672		Rev 3790
1	/*	1	/*
2	* Copyright (c) 2006 Jakub Jermar	2	* Copyright (c) 2006 Jakub Jermar
3	* All rights reserved.	3	* All rights reserved.
4	*	4	*
5	* Redistribution and use in source and binary forms, with or without	5	* Redistribution and use in source and binary forms, with or without
6	* modification, are permitted provided that the following conditions	6	* modification, are permitted provided that the following conditions
7	* are met:	7	* are met:
8	*	8	*
9	* - Redistributions of source code must retain the above copyright	9	* - Redistributions of source code must retain the above copyright
10	* notice, this list of conditions and the following disclaimer.	10	* notice, this list of conditions and the following disclaimer.
11	* - Redistributions in binary form must reproduce the above copyright	11	* - Redistributions in binary form must reproduce the above copyright
12	* notice, this list of conditions and the following disclaimer in the	12	* notice, this list of conditions and the following disclaimer in the
13	* documentation and/or other materials provided with the distribution.	13	* documentation and/or other materials provided with the distribution.
14	* - The name of the author may not be used to endorse or promote products	14	* - The name of the author may not be used to endorse or promote products
15	* derived from this software without specific prior written permission.	15	* derived from this software without specific prior written permission.
16	*	16	*
17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27	*/	27	*/
28		28
29	/** @addtogroup sparc64	29	/** @addtogroup sparc64
30	* @{	30	* @{
31	*/	31	*/
32	/** @file	32	/** @file
33	*/	33	*/
34		34
35	#include <smp/ipi.h>	35	#include <smp/ipi.h>
36	#include <cpu.h>	36	#include <cpu.h>
37	#include <arch.h>	37	#include <arch.h>
38	#include <arch/cpu.h>	38	#include <arch/cpu.h>
39	#include <arch/asm.h>	39	#include <arch/asm.h>
40	#include <config.h>	40	#include <config.h>
41	#include <mm/tlb.h>	41	#include <mm/tlb.h>
42	#include <arch/interrupt.h>	42	#include <arch/interrupt.h>
43	#include <arch/trap/interrupt.h>	43	#include <arch/trap/interrupt.h>
44	#include <arch/barrier.h>	44	#include <arch/barrier.h>
45	#include <preemption.h>	45	#include <preemption.h>
46	#include <time/delay.h>	46	#include <time/delay.h>
47	#include <panic.h>	47	#include <panic.h>
48		48
49	/** Set the contents of the outgoing interrupt vector data.	49	/** Set the contents of the outgoing interrupt vector data.
50	*	50	*
51	* The first data item (data 0) will be set to the value of func, the	51	* The first data item (data 0) will be set to the value of func, the
52	* rest of the vector will contain zeros.	52	* rest of the vector will contain zeros.
53	*	53	*
54	* This is a helper function used from within the cross_call function.	54	* This is a helper function used from within the cross_call function.
55	*	55	*
56	* @param func value the first data item of the vector will be set to	56	* @param func value the first data item of the vector will be set to
57	*/	57	*/
58	static inline void set_intr_w_data(void (* func)(void))	58	static inline void set_intr_w_data(void (* func)(void))
59	{	59	{
60	#if defined (US)	60	#if defined (US)
61	asi_u64_write(ASI_INTR_W, ASI_UDB_INTR_W_DATA_0, (uintptr_t) func);	61	asi_u64_write(ASI_INTR_W, ASI_UDB_INTR_W_DATA_0, (uintptr_t) func);
62	asi_u64_write(ASI_INTR_W, ASI_UDB_INTR_W_DATA_1, 0);	62	asi_u64_write(ASI_INTR_W, ASI_UDB_INTR_W_DATA_1, 0);
63	asi_u64_write(ASI_INTR_W, ASI_UDB_INTR_W_DATA_2, 0);	63	asi_u64_write(ASI_INTR_W, ASI_UDB_INTR_W_DATA_2, 0);
64	#elif defined (US3)	64	#elif defined (US3)
65	asi_u64_write(ASI_INTR_W, VA_INTR_W_DATA_0, (uintptr_t) func);	65	asi_u64_write(ASI_INTR_W, VA_INTR_W_DATA_0, (uintptr_t) func);
66	asi_u64_write(ASI_INTR_W, VA_INTR_W_DATA_1, 0);	66	asi_u64_write(ASI_INTR_W, VA_INTR_W_DATA_1, 0);
67	asi_u64_write(ASI_INTR_W, VA_INTR_W_DATA_2, 0);	67	asi_u64_write(ASI_INTR_W, VA_INTR_W_DATA_2, 0);
68	asi_u64_write(ASI_INTR_W, VA_INTR_W_DATA_3, 0);	68	asi_u64_write(ASI_INTR_W, VA_INTR_W_DATA_3, 0);
69	asi_u64_write(ASI_INTR_W, VA_INTR_W_DATA_4, 0);	69	asi_u64_write(ASI_INTR_W, VA_INTR_W_DATA_4, 0);
70	asi_u64_write(ASI_INTR_W, VA_INTR_W_DATA_5, 0);	70	asi_u64_write(ASI_INTR_W, VA_INTR_W_DATA_5, 0);
71	asi_u64_write(ASI_INTR_W, VA_INTR_W_DATA_6, 0);	71	asi_u64_write(ASI_INTR_W, VA_INTR_W_DATA_6, 0);
72	asi_u64_write(ASI_INTR_W, VA_INTR_W_DATA_7, 0);	72	asi_u64_write(ASI_INTR_W, VA_INTR_W_DATA_7, 0);
73	#endif	73	#endif
74	}	74	}
75		75
76	/** Invoke function on another processor.	76	/** Invoke function on another processor.
77	*	77	*
78	* Currently, only functions without arguments are supported.	78	* Currently, only functions without arguments are supported.
79	* Supporting more arguments in the future should be no big deal.	79	* Supporting more arguments in the future should be no big deal.
80	*	80	*
81	* Interrupts must be disabled prior to this call.	81	* Interrupts must be disabled prior to this call.
82	*	82	*
83	* @param mid MID of the target processor.	83	* @param mid MID of the target processor.
84	* @param func Function to be invoked.	84	* @param func Function to be invoked.
85	*/	85	*/
86	static void cross_call(int mid, void (* func)(void))	86	static void cross_call(int mid, void (* func)(void))
87	{	87	{
88	uint64_t status;	88	uint64_t status;
89	bool done;	89	bool done;
90		90
91	/*	91	/*
92	* This function might enable interrupts for a while.	92	* This function might enable interrupts for a while.
93	* In order to prevent migration to another processor,	93	* In order to prevent migration to another processor,
94	* we explicitly disable preemption.	94	* we explicitly disable preemption.
95	*/	95	*/
96		96
97	preemption_disable();	97	preemption_disable();
98		98
99	status = asi_u64_read(ASI_INTR_DISPATCH_STATUS, 0);	99	status = asi_u64_read(ASI_INTR_DISPATCH_STATUS, 0);
100	if (status & INTR_DISPATCH_STATUS_BUSY)	100	if (status & INTR_DISPATCH_STATUS_BUSY)
101	panic("Interrupt Dispatch Status busy bit set\n");	101	panic("Interrupt Dispatch Status busy bit set.");
102		102
103	ASSERT(!(pstate_read() & PSTATE_IE_BIT));	103	ASSERT(!(pstate_read() & PSTATE_IE_BIT));
104		104
105	do {	105	do {
106	set_intr_w_data(func);	106	set_intr_w_data(func);
107	asi_u64_write(ASI_INTR_W,	107	asi_u64_write(ASI_INTR_W,
108	(mid << INTR_VEC_DISPATCH_MID_SHIFT) \|	108	(mid << INTR_VEC_DISPATCH_MID_SHIFT) \|
109	VA_INTR_W_DISPATCH, 0);	109	VA_INTR_W_DISPATCH, 0);
110		110
111	membar();	111	membar();
112		112
113	do {	113	do {
114	status = asi_u64_read(ASI_INTR_DISPATCH_STATUS, 0);	114	status = asi_u64_read(ASI_INTR_DISPATCH_STATUS, 0);
115	} while (status & INTR_DISPATCH_STATUS_BUSY);	115	} while (status & INTR_DISPATCH_STATUS_BUSY);
116		116
117	done = !(status & INTR_DISPATCH_STATUS_NACK);	117	done = !(status & INTR_DISPATCH_STATUS_NACK);
118	if (!done) {	118	if (!done) {
119	/*	119	/*
120	* Prevent deadlock.	120	* Prevent deadlock.
121	*/	121	*/
122	(void) interrupts_enable();	122	(void) interrupts_enable();
123	delay(20 + (tick_read() & 0xff));	123	delay(20 + (tick_read() & 0xff));
124	(void) interrupts_disable();	124	(void) interrupts_disable();
125	}	125	}
126	} while (done);	126	} while (done);
127		127
128	preemption_enable();	128	preemption_enable();
129	}	129	}
130		130
131	/*	131	/*
132	* Deliver IPI to all processors except the current one.	132	* Deliver IPI to all processors except the current one.
133	*	133	*
134	* The sparc64 architecture does not support any group addressing	134	* The sparc64 architecture does not support any group addressing
135	* which is found, for instance, on ia32 and amd64. Therefore we	135	* which is found, for instance, on ia32 and amd64. Therefore we
136	* need to simulate the broadcast by sending the message to	136	* need to simulate the broadcast by sending the message to
137	* all target processors step by step.	137	* all target processors step by step.
138	*	138	*
139	* We assume that interrupts are disabled.	139	* We assume that interrupts are disabled.
140	*	140	*
141	* @param ipi IPI number.	141	* @param ipi IPI number.
142	*/	142	*/
143	void ipi_broadcast_arch(int ipi)	143	void ipi_broadcast_arch(int ipi)
144	{	144	{
145	unsigned int i;	145	unsigned int i;
146		146
147	void (* func)(void);	147	void (* func)(void);
148		148
149	switch (ipi) {	149	switch (ipi) {
150	case IPI_TLB_SHOOTDOWN:	150	case IPI_TLB_SHOOTDOWN:
151	func = tlb_shootdown_ipi_recv;	151	func = tlb_shootdown_ipi_recv;
152	break;	152	break;
153	default:	153	default:
154	panic("Unknown IPI (%d).\n", ipi);	154	panic("Unknown IPI (%d).", ipi);
155	break;	155	break;
156	}	156	}
157		157
158	/*	158	/*
159	* As long as we don't support hot-plugging	159	* As long as we don't support hot-plugging
160	* or hot-unplugging of CPUs, we can walk	160	* or hot-unplugging of CPUs, we can walk
161	* the cpus array and read processor's MID	161	* the cpus array and read processor's MID
162	* without locking.	162	* without locking.
163	*/	163	*/
164		164
165	for (i = 0; i < config.cpu_active; i++) {	165	for (i = 0; i < config.cpu_active; i++) {
166	if (&cpus[i] == CPU)	166	if (&cpus[i] == CPU)
167	continue; /* skip the current CPU */	167	continue; /* skip the current CPU */
168		168
169	cross_call(cpus[i].arch.mid, func);	169	cross_call(cpus[i].arch.mid, func);
170	}	170	}
171	}	171	}
172		172
173	/** @}	173	/** @}
174	*/	174	*/
175		175