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Line 59... Line 59...
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    count_t cnt;
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    count_t cnt;
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    ASSERT(as->arch.itsb && as->arch.dtsb);
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    ASSERT(as->arch.itsb && as->arch.dtsb);
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    i0 = (page >> MMU_PAGE_WIDTH) & TSB_INDEX_MASK;
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    i0 = (page >> MMU_PAGE_WIDTH) & TSB_INDEX_MASK;
-
 
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    ASSERT(i0 < ITSB_ENTRY_COUNT && i0 < DTSB_ENTRY_COUNT);
-
 
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    if (pages == (count_t) -1 || (pages * 2) > ITSB_ENTRY_COUNT)
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    if (pages == (count_t) -1 || (pages * 2) > ITSB_ENTRY_COUNT)
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        cnt = ITSB_ENTRY_COUNT;
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        cnt = ITSB_ENTRY_COUNT;
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    else
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    else
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        cnt = pages * 2;
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        cnt = pages * 2;
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Line 82... Line 84...
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void itsb_pte_copy(pte_t *t, index_t index)
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void itsb_pte_copy(pte_t *t, index_t index)
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{
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{
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    as_t *as;
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    as_t *as;
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    tsb_entry_t *tsb;
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    tsb_entry_t *tsb;
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    index_t entry;
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    index_t entry;
-
 
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-
 
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    ASSERT(index <= 1);
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    as = t->as;
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    as = t->as;
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    entry = ((t->page >> MMU_PAGE_WIDTH) + index) & TSB_INDEX_MASK;
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    entry = ((t->page >> MMU_PAGE_WIDTH) + index) & TSB_INDEX_MASK;
-
 
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    ASSERT(entry < ITSB_ENTRY_COUNT);
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    tsb = &as->arch.itsb[entry];
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    tsb = &as->arch.itsb[entry];
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    /*
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    /*
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     * We use write barriers to make sure that the TSB load
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     * We use write barriers to make sure that the TSB load
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     * won't use inconsistent data or that the fault will
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     * won't use inconsistent data or that the fault will
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                     * set to 0) */
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                     * set to 0) */
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    write_barrier();
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    write_barrier();
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    tsb->tag.context = as->asid;
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    tsb->tag.context = as->asid;
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    tsb->tag.va_tag = (t->page + (index << MMU_PAGE_WIDTH)) >>
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    /* the shift is bigger than PAGE_WIDTH, do not bother with index  */
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        VA_TAG_PAGE_SHIFT;
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    tsb->tag.va_tag = t->page >> VA_TAG_PAGE_SHIFT;
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    tsb->data.value = 0;
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    tsb->data.value = 0;
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    tsb->data.size = PAGESIZE_8K;
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    tsb->data.size = PAGESIZE_8K;
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    tsb->data.pfn = (t->frame >> MMU_FRAME_WIDTH) + index;
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    tsb->data.pfn = (t->frame >> MMU_FRAME_WIDTH) + index;
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    tsb->data.cp = t->c;
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    tsb->data.cp = t->c;
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    tsb->data.p = t->k;     /* p as privileged */
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    tsb->data.p = t->k;     /* p as privileged */
Line 126... Line 131...
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{
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{
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    as_t *as;
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    as_t *as;
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    tsb_entry_t *tsb;
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    tsb_entry_t *tsb;
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    index_t entry;
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    index_t entry;
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135
   
-
 
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    ASSERT(index <= 1);
-
 
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    as = t->as;
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    as = t->as;
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    entry = ((t->page >> MMU_PAGE_WIDTH) + index) & TSB_INDEX_MASK;
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    entry = ((t->page >> MMU_PAGE_WIDTH) + index) & TSB_INDEX_MASK;
-
 
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    ASSERT(entry < DTSB_ENTRY_COUNT);
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    tsb = &as->arch.dtsb[entry];
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    tsb = &as->arch.dtsb[entry];
134
 
142
 
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    /*
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    /*
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     * We use write barriers to make sure that the TSB load
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     * We use write barriers to make sure that the TSB load
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     * won't use inconsistent data or that the fault will
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     * won't use inconsistent data or that the fault will
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                     * set to 0) */
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                     * set to 0) */
144
 
152
 
145
    write_barrier();
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    write_barrier();
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154
 
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    tsb->tag.context = as->asid;
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    tsb->tag.context = as->asid;
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    tsb->tag.va_tag = (t->page + (index << MMU_PAGE_WIDTH)) >>
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    /* the shift is bigger than PAGE_WIDTH, do not bother with index */
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        VA_TAG_PAGE_SHIFT;
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    tsb->tag.va_tag = t->page >> VA_TAG_PAGE_SHIFT;
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    tsb->data.value = 0;
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    tsb->data.value = 0;
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    tsb->data.size = PAGESIZE_8K;
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    tsb->data.size = PAGESIZE_8K;
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    tsb->data.pfn = (t->frame >> MMU_FRAME_WIDTH) + index;
160
    tsb->data.pfn = (t->frame >> MMU_FRAME_WIDTH) + index;
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    tsb->data.cp = t->c;
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    tsb->data.cp = t->c;
154
#ifdef CONFIG_VIRT_IDX_DCACHE
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#ifdef CONFIG_VIRT_IDX_DCACHE