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Line 59... Line 59...
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    count_t cnt;
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    count_t cnt;
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    ASSERT(as->arch.itsb && as->arch.dtsb);
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    ASSERT(as->arch.itsb && as->arch.dtsb);
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    i0 = (page >> MMU_PAGE_WIDTH) & TSB_INDEX_MASK;
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    i0 = (page >> MMU_PAGE_WIDTH) & TSB_INDEX_MASK;
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    cnt = min(pages * MMU_PAGES_PER_PAGE, ITSB_ENTRY_COUNT);
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    if (pages == (count_t) -1 || (pages * 2) > ITSB_ENTRY_COUNT)
-
 
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        cnt = ITSB_ENTRY_COUNT;
-
 
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    else
-
 
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        cnt = pages * 2;
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    for (i = 0; i < cnt; i++) {
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    for (i = 0; i < cnt; i++) {
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        as->arch.itsb[(i0 + i) & (ITSB_ENTRY_COUNT - 1)].tag.invalid =
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        as->arch.itsb[(i0 + i) & (ITSB_ENTRY_COUNT - 1)].tag.invalid =
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            true;
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            true;
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        as->arch.dtsb[(i0 + i) & (DTSB_ENTRY_COUNT - 1)].tag.invalid =
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        as->arch.dtsb[(i0 + i) & (DTSB_ENTRY_COUNT - 1)].tag.invalid =
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    tsb->data.w = ro ? false : t->w;
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    tsb->data.w = ro ? false : t->w;
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    tsb->data.v = t->p;
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    tsb->data.v = t->p;
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    write_barrier();
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    write_barrier();
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    tsb->tag.invalid = true;    /* mark the entry as valid */
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    tsb->tag.invalid = false;   /* mark the entry as valid */
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}
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}
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/** @}
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/** @}
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 */
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 */