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 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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 */
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 */
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 /** @addtogroup sparc64mm 
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/** @addtogroup sparc64mm  
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 * @{
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 * @{
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 */
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 */
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/** @file
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/** @file
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 */
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 */
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    "Secondary",
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    "Secondary",
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    "Nucleus",
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    "Nucleus",
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    "Reserved"
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    "Reserved"
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};
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};
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/** Initialize ITLB and DTLB.
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 *
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 * The goal of this function is to disable MMU
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 * so that both TLBs can be purged and new
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 * kernel 4M locked entry can be installed.
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 * After TLB is initialized, MMU is enabled
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 * again.
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 *
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 * Switching MMU off imposes the requirement for
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 * the kernel to run in identity mapped environment.
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 */
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void tlb_arch_init(void)
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void tlb_arch_init(void)
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{
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{
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    tlb_tag_access_reg_t tag;
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    tlb_data_t data;
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    frame_address_t fr;
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    page_address_t pg;
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    fr.address = config.base;
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    pg.address = config.base;
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    immu_disable();
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    dmmu_disable();
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    /*
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     * Demap everything, especially OpenFirmware.
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     */
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    itlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_NUCLEUS, 0);
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    dtlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_NUCLEUS, 0);
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    /*
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     * We do identity mapping of 4M-page at 4M.
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     */
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    tag.value = ASID_KERNEL;
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    tag.vpn = pg.vpn;
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    itlb_tag_access_write(tag.value);
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    dtlb_tag_access_write(tag.value);
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    data.value = 0;
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    data.v = true;
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    data.size = PAGESIZE_4M;
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    data.pfn = fr.pfn;
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    data.l = true;
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    data.cp = 1;
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    data.cv = 1;
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    data.p = true;
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    data.w = true;
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    data.g = true;
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    itlb_data_in_write(data.value);
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    dtlb_data_in_write(data.value);
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    /*
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     * Register window traps can occur before MMU is enabled again.
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     * This ensures that any such traps will be handled from
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     * kernel identity mapped trap handler.
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     */
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    trap_switch_trap_table();
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    tlb_invalidate_all();
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    dmmu_enable();
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    immu_enable();
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}
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}
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/** Insert privileged mapping into DMMU TLB.
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/** Insert privileged mapping into DMMU TLB.
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 *
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 *
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 * @param page Virtual page address.
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 * @param page Virtual page address.
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        itlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_NUCLEUS, page + i * PAGE_SIZE);
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        itlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_NUCLEUS, page + i * PAGE_SIZE);
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        dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_NUCLEUS, page + i * PAGE_SIZE);
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        dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_NUCLEUS, page + i * PAGE_SIZE);
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    }
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    }
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}
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}
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 /** @}
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/** @}
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 */
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 */
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 -