WebSVN – HelenOS – Diff – /trunk/kernel/arch/sparc64/include/trap/interrupt.h


/*
 * Copyright (c) 2005 Jakub Jermar
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * - Redistributions of source code must retain the above copyright
 *   notice, this list of conditions and the following disclaimer.
 * - Redistributions in binary form must reproduce the above copyright
 *   notice, this list of conditions and the following disclaimer in the
 *   documentation and/or other materials provided with the distribution.
 * - The name of the author may not be used to endorse or promote products
 *   derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
/** @addtogroup sparc64interrupt
 * @{
 */
/**
 * @file
 * @brief This file contains interrupt vector trap handler.
 */
 
#ifndef KERN_sparc64_TRAP_INTERRUPT_H_
#define KERN_sparc64_TRAP_INTERRUPT_H_
 
#include <arch/trap/trap_table.h>
#include <arch/stack.h>
 
/* IMAP register bits */
#define IGN_MASK    0x7c0
#define INO_MASK    0x1f
#define IMAP_V_MASK (1ULL << 31)
 
#define IGN_SHIFT   6
 
 
/* Interrupt ASI registers. */
#define ASI_UDB_INTR_W          0x77
#define ASI_INTR_DISPATCH_STATUS    0x48
#define ASI_UDB_INTR_R          0x7f
#define ASI_INTR_RECEIVE        0x49
 
/* VA's used with ASI_UDB_INTR_W register. */
#define ASI_UDB_INTR_W_DATA_0   0x40
#define ASI_UDB_INTR_W_DATA_1   0x50
#define ASI_UDB_INTR_W_DATA_2   0x60
#define ASI_UDB_INTR_W_DISPATCH 0x70
 
/* VA's used with ASI_UDB_INTR_R register. */
#define ASI_UDB_INTR_R_DATA_0   0x40
#define ASI_UDB_INTR_R_DATA_1   0x50
#define ASI_UDB_INTR_R_DATA_2   0x60
 
/* Shifts in the Interrupt Vector Dispatch virtual address. */
#define INTR_VEC_DISPATCH_MID_SHIFT 14
 
/* Bits in the Interrupt Dispatch Status register. */
#define INTR_DISPATCH_STATUS_NACK   0x2
#define INTR_DISPATCH_STATUS_BUSY   0x1
 
#define TT_INTERRUPT_LEVEL_1            0x41
#define TT_INTERRUPT_LEVEL_2            0x42
#define TT_INTERRUPT_LEVEL_3            0x43
#define TT_INTERRUPT_LEVEL_4            0x44
#define TT_INTERRUPT_LEVEL_5            0x45
#define TT_INTERRUPT_LEVEL_6            0x46
#define TT_INTERRUPT_LEVEL_7            0x47
#define TT_INTERRUPT_LEVEL_8            0x48
#define TT_INTERRUPT_LEVEL_9            0x49
#define TT_INTERRUPT_LEVEL_10           0x4a
#define TT_INTERRUPT_LEVEL_11           0x4b
#define TT_INTERRUPT_LEVEL_12           0x4c
#define TT_INTERRUPT_LEVEL_13           0x4d
#define TT_INTERRUPT_LEVEL_14           0x4e
#define TT_INTERRUPT_LEVEL_15           0x4f
 
#define TT_INTERRUPT_VECTOR_TRAP        0x60
 
#define INTERRUPT_LEVEL_N_HANDLER_SIZE      TRAP_TABLE_ENTRY_SIZE
#define INTERRUPT_VECTOR_TRAP_HANDLER_SIZE  TRAP_TABLE_ENTRY_SIZE
 
#ifdef __ASM__
.macro INTERRUPT_LEVEL_N_HANDLER n
    mov \n - 1, %g2
    PREEMPTIBLE_HANDLER exc_dispatch
.endm
 
.macro INTERRUPT_VECTOR_TRAP_HANDLER
    PREEMPTIBLE_HANDLER interrupt
.endm
#endif /* __ASM__ */
 
#ifndef __ASM__
extern void interrupt(int n, istate_t *istate);
#endif /* !def __ASM__ */
 
#endif
 
/** @}
 */
 

Subversion Repositories HelenOS

(root)/trunk/kernel/arch/sparc64/include/trap/interrupt.h – Rev 2068 → 2071

Rev 2068		Rev 2071
1	/*	1	/*
2	* Copyright (C) 2005 Jakub Jermar	2	* Copyright (c) 2005 Jakub Jermar
3	* All rights reserved.	3	* All rights reserved.
4	*	4	*
5	* Redistribution and use in source and binary forms, with or without	5	* Redistribution and use in source and binary forms, with or without
6	* modification, are permitted provided that the following conditions	6	* modification, are permitted provided that the following conditions
7	* are met:	7	* are met:
8	*	8	*
9	* - Redistributions of source code must retain the above copyright	9	* - Redistributions of source code must retain the above copyright
10	* notice, this list of conditions and the following disclaimer.	10	* notice, this list of conditions and the following disclaimer.
11	* - Redistributions in binary form must reproduce the above copyright	11	* - Redistributions in binary form must reproduce the above copyright
12	* notice, this list of conditions and the following disclaimer in the	12	* notice, this list of conditions and the following disclaimer in the
13	* documentation and/or other materials provided with the distribution.	13	* documentation and/or other materials provided with the distribution.
14	* - The name of the author may not be used to endorse or promote products	14	* - The name of the author may not be used to endorse or promote products
15	* derived from this software without specific prior written permission.	15	* derived from this software without specific prior written permission.
16	*	16	*
17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27	*/	27	*/
28		28
29	/** @addtogroup sparc64interrupt	29	/** @addtogroup sparc64interrupt
30	* @{	30	* @{
31	*/	31	*/
32	/**	32	/**
33	* @file	33	* @file
34	* @brief This file contains interrupt vector trap handler.	34	* @brief This file contains interrupt vector trap handler.
35	*/	35	*/
36		36
37	#ifndef KERN_sparc64_TRAP_INTERRUPT_H_	37	#ifndef KERN_sparc64_TRAP_INTERRUPT_H_
38	#define KERN_sparc64_TRAP_INTERRUPT_H_	38	#define KERN_sparc64_TRAP_INTERRUPT_H_
39		39
40	#include <arch/trap/trap_table.h>	40	#include <arch/trap/trap_table.h>
41	#include <arch/stack.h>	41	#include <arch/stack.h>
42		42
43	/* IMAP register bits */	43	/* IMAP register bits */
44	#define IGN_MASK 0x7c0	44	#define IGN_MASK 0x7c0
45	#define INO_MASK 0x1f	45	#define INO_MASK 0x1f
46	#define IMAP_V_MASK (1ULL << 31)	46	#define IMAP_V_MASK (1ULL << 31)
47		47
48	#define IGN_SHIFT 6	48	#define IGN_SHIFT 6
49		49
50		50
51	/* Interrupt ASI registers. */	51	/* Interrupt ASI registers. */
52	#define ASI_UDB_INTR_W 0x77	52	#define ASI_UDB_INTR_W 0x77
53	#define ASI_INTR_DISPATCH_STATUS 0x48	53	#define ASI_INTR_DISPATCH_STATUS 0x48
54	#define ASI_UDB_INTR_R 0x7f	54	#define ASI_UDB_INTR_R 0x7f
55	#define ASI_INTR_RECEIVE 0x49	55	#define ASI_INTR_RECEIVE 0x49
56		56
57	/* VA's used with ASI_UDB_INTR_W register. */	57	/* VA's used with ASI_UDB_INTR_W register. */
58	#define ASI_UDB_INTR_W_DATA_0 0x40	58	#define ASI_UDB_INTR_W_DATA_0 0x40
59	#define ASI_UDB_INTR_W_DATA_1 0x50	59	#define ASI_UDB_INTR_W_DATA_1 0x50
60	#define ASI_UDB_INTR_W_DATA_2 0x60	60	#define ASI_UDB_INTR_W_DATA_2 0x60
61	#define ASI_UDB_INTR_W_DISPATCH 0x70	61	#define ASI_UDB_INTR_W_DISPATCH 0x70
62		62
63	/* VA's used with ASI_UDB_INTR_R register. */	63	/* VA's used with ASI_UDB_INTR_R register. */
64	#define ASI_UDB_INTR_R_DATA_0 0x40	64	#define ASI_UDB_INTR_R_DATA_0 0x40
65	#define ASI_UDB_INTR_R_DATA_1 0x50	65	#define ASI_UDB_INTR_R_DATA_1 0x50
66	#define ASI_UDB_INTR_R_DATA_2 0x60	66	#define ASI_UDB_INTR_R_DATA_2 0x60
67		67
68	/* Shifts in the Interrupt Vector Dispatch virtual address. */	68	/* Shifts in the Interrupt Vector Dispatch virtual address. */
69	#define INTR_VEC_DISPATCH_MID_SHIFT 14	69	#define INTR_VEC_DISPATCH_MID_SHIFT 14
70		70
71	/* Bits in the Interrupt Dispatch Status register. */	71	/* Bits in the Interrupt Dispatch Status register. */
72	#define INTR_DISPATCH_STATUS_NACK 0x2	72	#define INTR_DISPATCH_STATUS_NACK 0x2
73	#define INTR_DISPATCH_STATUS_BUSY 0x1	73	#define INTR_DISPATCH_STATUS_BUSY 0x1
74		74
75	#define TT_INTERRUPT_LEVEL_1 0x41	75	#define TT_INTERRUPT_LEVEL_1 0x41
76	#define TT_INTERRUPT_LEVEL_2 0x42	76	#define TT_INTERRUPT_LEVEL_2 0x42
77	#define TT_INTERRUPT_LEVEL_3 0x43	77	#define TT_INTERRUPT_LEVEL_3 0x43
78	#define TT_INTERRUPT_LEVEL_4 0x44	78	#define TT_INTERRUPT_LEVEL_4 0x44
79	#define TT_INTERRUPT_LEVEL_5 0x45	79	#define TT_INTERRUPT_LEVEL_5 0x45
80	#define TT_INTERRUPT_LEVEL_6 0x46	80	#define TT_INTERRUPT_LEVEL_6 0x46
81	#define TT_INTERRUPT_LEVEL_7 0x47	81	#define TT_INTERRUPT_LEVEL_7 0x47
82	#define TT_INTERRUPT_LEVEL_8 0x48	82	#define TT_INTERRUPT_LEVEL_8 0x48
83	#define TT_INTERRUPT_LEVEL_9 0x49	83	#define TT_INTERRUPT_LEVEL_9 0x49
84	#define TT_INTERRUPT_LEVEL_10 0x4a	84	#define TT_INTERRUPT_LEVEL_10 0x4a
85	#define TT_INTERRUPT_LEVEL_11 0x4b	85	#define TT_INTERRUPT_LEVEL_11 0x4b
86	#define TT_INTERRUPT_LEVEL_12 0x4c	86	#define TT_INTERRUPT_LEVEL_12 0x4c
87	#define TT_INTERRUPT_LEVEL_13 0x4d	87	#define TT_INTERRUPT_LEVEL_13 0x4d
88	#define TT_INTERRUPT_LEVEL_14 0x4e	88	#define TT_INTERRUPT_LEVEL_14 0x4e
89	#define TT_INTERRUPT_LEVEL_15 0x4f	89	#define TT_INTERRUPT_LEVEL_15 0x4f
90		90
91	#define TT_INTERRUPT_VECTOR_TRAP 0x60	91	#define TT_INTERRUPT_VECTOR_TRAP 0x60
92		92
93	#define INTERRUPT_LEVEL_N_HANDLER_SIZE TRAP_TABLE_ENTRY_SIZE	93	#define INTERRUPT_LEVEL_N_HANDLER_SIZE TRAP_TABLE_ENTRY_SIZE
94	#define INTERRUPT_VECTOR_TRAP_HANDLER_SIZE TRAP_TABLE_ENTRY_SIZE	94	#define INTERRUPT_VECTOR_TRAP_HANDLER_SIZE TRAP_TABLE_ENTRY_SIZE
95		95
96	#ifdef __ASM__	96	#ifdef __ASM__
97	.macro INTERRUPT_LEVEL_N_HANDLER n	97	.macro INTERRUPT_LEVEL_N_HANDLER n
98	mov \n - 1, %g2	98	mov \n - 1, %g2
99	PREEMPTIBLE_HANDLER exc_dispatch	99	PREEMPTIBLE_HANDLER exc_dispatch
100	.endm	100	.endm
101		101
102	.macro INTERRUPT_VECTOR_TRAP_HANDLER	102	.macro INTERRUPT_VECTOR_TRAP_HANDLER
103	PREEMPTIBLE_HANDLER interrupt	103	PREEMPTIBLE_HANDLER interrupt
104	.endm	104	.endm
105	#endif /* __ASM__ */	105	#endif /* __ASM__ */
106		106
107	#ifndef __ASM__	107	#ifndef __ASM__
108	extern void interrupt(int n, istate_t *istate);	108	extern void interrupt(int n, istate_t *istate);
109	#endif /* !def __ASM__ */	109	#endif /* !def __ASM__ */
110		110
111	#endif	111	#endif
112		112
113	/** @}	113	/** @}
114	*/	114	*/
115		115