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Line 63... Line 63...
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#define TLB_DEMAP_CONTEXT_SHIFT 4
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#define TLB_DEMAP_CONTEXT_SHIFT 4
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/* TLB Tag Access shifts */
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/* TLB Tag Access shifts */
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#define TLB_TAG_ACCESS_CONTEXT_SHIFT    0
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#define TLB_TAG_ACCESS_CONTEXT_SHIFT    0
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#define TLB_TAG_ACCESS_CONTEXT_MASK ((1<<13)-1)
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#define TLB_TAG_ACCESS_CONTEXT_MASK ((1 << 13) - 1)
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#define TLB_TAG_ACCESS_VPN_SHIFT    13
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#define TLB_TAG_ACCESS_VPN_SHIFT    13
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#ifndef __ASM__
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#ifndef __ASM__
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#include <arch/mm/tte.h>
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#include <arch/mm/tte.h>
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/** I-/D-TLB Tag Read Register. */
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/** I-/D-TLB Tag Read Register. */
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union tlb_tag_read_reg {
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union tlb_tag_read_reg {
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    uint64_t value;
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    uint64_t value;
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    struct {
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    struct {
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        uint64_t vpn : 51;      /**< Virtual Address bits 63:13. */
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        uint64_t vpn : 51;  /**< Virtual Address bits 63:13. */
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        unsigned context : 13;      /**< Context identifier. */
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        unsigned context : 13;  /**< Context identifier. */
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    } __attribute__ ((packed));
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    } __attribute__ ((packed));
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};
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};
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typedef union tlb_tag_read_reg tlb_tag_read_reg_t;
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typedef union tlb_tag_read_reg tlb_tag_read_reg_t;
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typedef union tlb_tag_read_reg tlb_tag_access_reg_t;
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typedef union tlb_tag_read_reg tlb_tag_access_reg_t;
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}
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}
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/** Perform IMMU TLB Demap Operation.
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/** Perform IMMU TLB Demap Operation.
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 *
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 *
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 * @param type Selects between context and page demap.
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 * @param type Selects between context and page demap.
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 * @param context_encoding Specifies which Context register has Context ID for demap.
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 * @param context_encoding Specifies which Context register has Context ID for
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 *  demap.
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 * @param page Address which is on the page to be demapped.
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 * @param page Address which is on the page to be demapped.
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 */
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 */
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static inline void itlb_demap(int type, int context_encoding, uintptr_t page)
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static inline void itlb_demap(int type, int context_encoding, uintptr_t page)
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{
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{
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    tlb_demap_addr_t da;
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    tlb_demap_addr_t da;
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    da.type = type;
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    da.type = type;
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    da.context = context_encoding;
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    da.context = context_encoding;
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    da.vpn = pg.vpn;
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    da.vpn = pg.vpn;
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    asi_u64_write(ASI_IMMU_DEMAP, da.value, 0); /* da.value is the address within the ASI */
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    asi_u64_write(ASI_IMMU_DEMAP, da.value, 0); /* da.value is the
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                             * address within the
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                             * ASI */
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    flush();
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    flush();
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}
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}
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/** Perform DMMU TLB Demap Operation.
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/** Perform DMMU TLB Demap Operation.
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 *
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 *
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 * @param type Selects between context and page demap.
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 * @param type Selects between context and page demap.
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 * @param context_encoding Specifies which Context register has Context ID for demap.
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 * @param context_encoding Specifies which Context register has Context ID for
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 *   demap.
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 * @param page Address which is on the page to be demapped.
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 * @param page Address which is on the page to be demapped.
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 */
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 */
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static inline void dtlb_demap(int type, int context_encoding, uintptr_t page)
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static inline void dtlb_demap(int type, int context_encoding, uintptr_t page)
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{
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{
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    tlb_demap_addr_t da;
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    tlb_demap_addr_t da;
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    da.type = type;
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    da.type = type;
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    da.context = context_encoding;
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    da.context = context_encoding;
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    da.vpn = pg.vpn;
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    da.vpn = pg.vpn;
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    asi_u64_write(ASI_DMMU_DEMAP, da.value, 0); /* da.value is the address within the ASI */
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    asi_u64_write(ASI_DMMU_DEMAP, da.value, 0); /* da.value is the
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                             * address within the
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                             * ASI */
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    membar();
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    membar();
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}
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}
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extern void fast_instruction_access_mmu_miss(int n, istate_t *istate);
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extern void fast_instruction_access_mmu_miss(int n, istate_t *istate);
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extern void fast_data_access_mmu_miss(int n, istate_t *istate);
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extern void fast_data_access_mmu_miss(int n, istate_t *istate);