Subversion Repositories HelenOS

Rev

Rev 1860 | Rev 2071 | Go to most recent revision | Show entire file | Ignore whitespace | Details | Blame | Last modification | View Log | RSS feed

Rev 1860 Rev 1891
Line 46... Line 46...
46 
#define ASI_ITLB_DATA_ACCESS_REG    0x55
 46 
#define ASI_ITLB_DATA_ACCESS_REG    0x55
47 
#define ASI_ITLB_TAG_READ_REG       0x56
 47 
#define ASI_ITLB_TAG_READ_REG       0x56
48 
#define ASI_IMMU_DEMAP          0x57
 48 
#define ASI_IMMU_DEMAP          0x57
49 
 
 49 
 
50 
/* Virtual Addresses within ASI_IMMU. */
 50 
/* Virtual Addresses within ASI_IMMU. */
51 
#define VA_IMMU_TAG_TARGET      0x0 /**< IMMU tag target register. */
 51 
#define VA_IMMU_TSB_TAG_TARGET      0x0 /**< IMMU TSB tag target register. */
52 
#define VA_IMMU_SFSR            0x18    /**< IMMU sync fault status register. */
 52 
#define VA_IMMU_SFSR            0x18    /**< IMMU sync fault status register. */
53 
#define VA_IMMU_TSB_BASE        0x28    /**< IMMU TSB base register. */
 53 
#define VA_IMMU_TSB_BASE        0x28    /**< IMMU TSB base register. */
54 
#define VA_IMMU_TAG_ACCESS      0x30    /**< IMMU TLB tag access register. */
 54 
#define VA_IMMU_TAG_ACCESS      0x30    /**< IMMU TLB tag access register. */
55 
 
 55 
 
56 
/* D-MMU ASIs. */
 56 
/* D-MMU ASIs. */
Line 62... Line 62...
62 
#define ASI_DTLB_DATA_ACCESS_REG    0x5d
 62 
#define ASI_DTLB_DATA_ACCESS_REG    0x5d
63 
#define ASI_DTLB_TAG_READ_REG       0x5e
 63 
#define ASI_DTLB_TAG_READ_REG       0x5e
64 
#define ASI_DMMU_DEMAP          0x5f
 64 
#define ASI_DMMU_DEMAP          0x5f
65 
 
 65 
 
66 
/* Virtual Addresses within ASI_DMMU. */
 66 
/* Virtual Addresses within ASI_DMMU. */
67 
#define VA_DMMU_TAG_TARGET      0x0 /**< DMMU tag target register. */
 67 
#define VA_DMMU_TSB_TAG_TARGET      0x0 /**< DMMU TSB tag target register. */
68 
#define VA_PRIMARY_CONTEXT_REG      0x8 /**< DMMU primary context register. */
 68 
#define VA_PRIMARY_CONTEXT_REG      0x8 /**< DMMU primary context register. */
69 
#define VA_SECONDARY_CONTEXT_REG    0x10    /**< DMMU secondary context register. */
 69 
#define VA_SECONDARY_CONTEXT_REG    0x10    /**< DMMU secondary context register. */
70 
#define VA_DMMU_SFSR            0x18    /**< DMMU sync fault status register. */
 70 
#define VA_DMMU_SFSR            0x18    /**< DMMU sync fault status register. */
71 
#define VA_DMMU_SFAR            0x20    /**< DMMU sync fault address register. */
 71 
#define VA_DMMU_SFAR            0x20    /**< DMMU sync fault address register. */
72 
#define VA_DMMU_TSB_BASE        0x28    /**< DMMU TSB base register. */
 72 
#define VA_DMMU_TSB_BASE        0x28    /**< DMMU TSB base register. */