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| Rev 1875 | Rev 1921 | ||
|---|---|---|---|
| Line 89... | Line 89... | ||
| 89 | #define WR9_MIE (0x1<<3) /** Master Interrupt Enable. */ |
89 | #define WR9_MIE (0x1<<3) /** Master Interrupt Enable. */ |
| 90 | 90 | ||
| 91 | /* Read Register 0 */ |
91 | /* Read Register 0 */ |
| 92 | #define RR0_RCA (0x1<<0) /** Receive Character Available. */ |
92 | #define RR0_RCA (0x1<<0) /** Receive Character Available. */ |
| 93 | 93 | ||
| - | 94 | /** Structure representing the z8530 device. */ |
|
| - | 95 | typedef struct { |
|
| - | 96 | devno_t devno; |
|
| - | 97 | volatile uint8_t *reg; /** Memory mapped registers of the z8530. */ |
|
| - | 98 | } z8530_t; |
|
| - | 99 | ||
| 94 | static inline void z8530_write(index_t chan, uint8_t reg, uint8_t val) |
100 | static inline void z8530_write(z8530_t *dev, index_t chan, uint8_t reg, uint8_t val) |
| 95 | { |
101 | { |
| 96 | /* |
102 | /* |
| 97 | * Registers 8-15 will automatically issue the Point High |
103 | * Registers 8-15 will automatically issue the Point High |
| 98 | * command as their bit 3 is 1. |
104 | * command as their bit 3 is 1. |
| 99 | */ |
105 | */ |
| 100 | kbd_virt_address[WR0+chan] = reg; /* select register */ |
106 | dev->reg[WR0+chan] = reg; /* select register */ |
| 101 | kbd_virt_address[WR0+chan] = val; /* write value */ |
107 | dev->reg[WR0+chan] = val; /* write value */ |
| 102 | } |
108 | } |
| 103 | 109 | ||
| 104 | static inline void z8530_write_a(uint8_t reg, uint8_t val) |
110 | static inline void z8530_write_a(z8530_t *dev, uint8_t reg, uint8_t val) |
| 105 | { |
111 | { |
| 106 | z8530_write(Z8530_CHAN_A, reg, val); |
112 | z8530_write(dev, Z8530_CHAN_A, reg, val); |
| 107 | } |
113 | } |
| 108 | static inline void z8530_write_b(uint8_t reg, uint8_t val) |
114 | static inline void z8530_write_b(z8530_t *dev, uint8_t reg, uint8_t val) |
| 109 | { |
115 | { |
| 110 | z8530_write(Z8530_CHAN_B, reg, val); |
116 | z8530_write(dev, Z8530_CHAN_B, reg, val); |
| 111 | } |
117 | } |
| 112 | 118 | ||
| 113 | static inline uint8_t z8530_read(index_t chan, uint8_t reg) |
119 | static inline uint8_t z8530_read(z8530_t *dev, index_t chan, uint8_t reg) |
| 114 | { |
120 | { |
| 115 | /* |
121 | /* |
| 116 | * Registers 8-15 will automatically issue the Point High |
122 | * Registers 8-15 will automatically issue the Point High |
| 117 | * command as their bit 3 is 1. |
123 | * command as their bit 3 is 1. |
| 118 | */ |
124 | */ |
| 119 | kbd_virt_address[WR0+chan] = reg; /* select register */ |
125 | dev->reg[WR0+chan] = reg; /* select register */ |
| 120 | return kbd_virt_address[WR0+chan]; |
126 | return dev->reg[WR0+chan]; |
| 121 | } |
127 | } |
| 122 | 128 | ||
| 123 | static inline uint8_t z8530_read_a(uint8_t reg) |
129 | static inline uint8_t z8530_read_a(z8530_t *dev, uint8_t reg) |
| 124 | { |
130 | { |
| 125 | return z8530_read(Z8530_CHAN_A, reg); |
131 | return z8530_read(dev, Z8530_CHAN_A, reg); |
| 126 | } |
132 | } |
| 127 | static inline uint8_t z8530_read_b(uint8_t reg) |
133 | static inline uint8_t z8530_read_b(z8530_t *dev, uint8_t reg) |
| 128 | { |
134 | { |
| 129 | return z8530_read(Z8530_CHAN_B, reg); |
135 | return z8530_read(dev, Z8530_CHAN_B, reg); |
| 130 | } |
136 | } |
| 131 | 137 | ||
| 132 | #endif |
138 | #endif |
| 133 | 139 | ||
| 134 | /** @} |
140 | /** @} |