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Rev 1849 Rev 1875
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#define RR13    13
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#define RR13    13
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#define RR14    14
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#define RR14    14
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#define RR15    15
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#define RR15    15
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/* Write Register 0 */
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/* Write Register 0 */
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#define WR0_TX_IP_RST   (0x5<<3)    /** Reset pending TX interrupt. */
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#define WR0_ERR_RST (0x6<<3)
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#define WR0_ERR_RST (0x6<<3)
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/* Write Register 1 */
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/* Write Register 1 */
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#define WR1_RID     (0x0<<3)    /** Receive Interrupts Disabled. */
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#define WR1_RID     (0x0<<3)    /** Receive Interrupts Disabled. */
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#define WR1_RIFCSC  (0x1<<3)    /** Receive Interrupt on First Character or Special Condition. */
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#define WR1_RIFCSC  (0x1<<3)    /** Receive Interrupt on First Character or Special Condition. */