WebSVN – HelenOS – Diff – /trunk/kernel/arch/sparc64/include/barrier.h


/*
 * Copyright (c) 2005 Jakub Jermar
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * - Redistributions of source code must retain the above copyright
 *   notice, this list of conditions and the following disclaimer.
 * - Redistributions in binary form must reproduce the above copyright
 *   notice, this list of conditions and the following disclaimer in the
 *   documentation and/or other materials provided with the distribution.
 * - The name of the author may not be used to endorse or promote products
 *   derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
/** @addtogroup sparc64
 * @{
 */
/** @file
 */
 
#ifndef KERN_sparc64_BARRIER_H_
#define KERN_sparc64_BARRIER_H_
 
/*
 * Our critical section barriers are prepared for the weakest RMO memory model.
 */
#define CS_ENTER_BARRIER()              \
    asm volatile (                  \
        "membar #LoadLoad | #LoadStore\n"   \
        ::: "memory"                \
    )
#define CS_LEAVE_BARRIER()              \
    asm volatile (                  \
        "membar #StoreStore\n"          \
        "membar #LoadStore\n"           \
        ::: "memory"                \
    )
 
#define memory_barrier()    \
    asm volatile ("membar #LoadLoad | #StoreStore\n" ::: "memory")
#define read_barrier()      \
    asm volatile ("membar #LoadLoad\n" ::: "memory")
#define write_barrier()     \
    asm volatile ("membar #StoreStore\n" ::: "memory")
 
static inline void flush(uintptr_t addr)
{
    asm volatile ("flush %0\n" :: "r" (addr) : "memory");
}
 
/** Flush Instruction Memory instruction. */
static inline void flush_blind(void)
{
    /*
     * The FLUSH instruction takes address parameter.
     * As such, it may trap if the address is not found in DTLB.
     *
     * The entire kernel text is mapped by a locked ITLB and
     * DTLB entries. Therefore, when this function is called,
     * the %o7 register will always be in the range mapped by
     * DTLB.
     */
     
        asm volatile ("flush %o7\n");
}
 
/** Memory Barrier instruction. */
static inline void membar(void)
{
    asm volatile ("membar #Sync\n");
}
 
#define smc_coherence(a)    \
{               \
    write_barrier();    \
    flush((a));     \
}
 
#endif
 
/** @}
 */
 

Rev 2272	Rev 3133
1	/*	1	/*
2	* Copyright (c) 2005 Jakub Jermar	2	* Copyright (c) 2005 Jakub Jermar
3	* All rights reserved.	3	* All rights reserved.
4	*	4	*
5	* Redistribution and use in source and binary forms, with or without	5	* Redistribution and use in source and binary forms, with or without
6	* modification, are permitted provided that the following conditions	6	* modification, are permitted provided that the following conditions
7	* are met:	7	* are met:
8	*	8	*
9	* - Redistributions of source code must retain the above copyright	9	* - Redistributions of source code must retain the above copyright
10	* notice, this list of conditions and the following disclaimer.	10	* notice, this list of conditions and the following disclaimer.
11	* - Redistributions in binary form must reproduce the above copyright	11	* - Redistributions in binary form must reproduce the above copyright
12	* notice, this list of conditions and the following disclaimer in the	12	* notice, this list of conditions and the following disclaimer in the
13	* documentation and/or other materials provided with the distribution.	13	* documentation and/or other materials provided with the distribution.
14	* - The name of the author may not be used to endorse or promote products	14	* - The name of the author may not be used to endorse or promote products
15	* derived from this software without specific prior written permission.	15	* derived from this software without specific prior written permission.
16	*	16	*
17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27	*/	27	*/
28		28
29	/** @addtogroup sparc64	29	/** @addtogroup sparc64
30	* @{	30	* @{
31	*/	31	*/
32	/** @file	32	/** @file
33	*/	33	*/
34		34
35	#ifndef KERN_sparc64_BARRIER_H_	35	#ifndef KERN_sparc64_BARRIER_H_
36	#define KERN_sparc64_BARRIER_H_	36	#define KERN_sparc64_BARRIER_H_
37		37
38	/*	38	/*
39	* Our critical section barriers are prepared for the weakest RMO memory model.	39	* Our critical section barriers are prepared for the weakest RMO memory model.
40	*/	40	*/
41	#define CS_ENTER_BARRIER() \	41	#define CS_ENTER_BARRIER() \
42	asm volatile ( \	42	asm volatile ( \
43	"membar #LoadLoad \| #LoadStore\n" \	43	"membar #LoadLoad \| #LoadStore\n" \
44	::: "memory" \	44	::: "memory" \
45	)	45	)
46	#define CS_LEAVE_BARRIER() \	46	#define CS_LEAVE_BARRIER() \
47	asm volatile ( \	47	asm volatile ( \
48	"membar #StoreStore\n" \	48	"membar #StoreStore\n" \
49	"membar #LoadStore\n" \	49	"membar #LoadStore\n" \
50	::: "memory" \	50	::: "memory" \
51	)	51	)
52		52
53	#define memory_barrier() \	53	#define memory_barrier() \
54	asm volatile ("membar #LoadLoad \| #StoreStore\n" ::: "memory")	54	asm volatile ("membar #LoadLoad \| #StoreStore\n" ::: "memory")
55	#define read_barrier() \	55	#define read_barrier() \
56	asm volatile ("membar #LoadLoad\n" ::: "memory")	56	asm volatile ("membar #LoadLoad\n" ::: "memory")
57	#define write_barrier() \	57	#define write_barrier() \
58	asm volatile ("membar #StoreStore\n" ::: "memory")	58	asm volatile ("membar #StoreStore\n" ::: "memory")
59		59
-		60	static inline void flush(uintptr_t addr)
-		61	{
-		62	asm volatile ("flush %0\n" :: "r" (addr) : "memory");
-		63	}
-		64
60	/** Flush Instruction Memory instruction. */	65	/** Flush Instruction Memory instruction. */
61	static inline void flush(void)	66	static inline void flush_blind(void)
62	{	67	{
63	/*	68	/*
64	* The FLUSH instruction takes address parameter.	69	* The FLUSH instruction takes address parameter.
65	* As such, it may trap if the address is not found in DTLB.	70	* As such, it may trap if the address is not found in DTLB.
66	*	71	*
67	* The entire kernel text is mapped by a locked ITLB and	72	* The entire kernel text is mapped by a locked ITLB and
68	* DTLB entries. Therefore, when this function is called,	73	* DTLB entries. Therefore, when this function is called,
69	* the %o7 register will always be in the range mapped by	74	* the %o7 register will always be in the range mapped by
70	* DTLB.	75	* DTLB.
71	*/	76	*/
72		77
73	asm volatile ("flush %o7\n");	78	asm volatile ("flush %o7\n");
74	}	79	}
75		80
76	/** Memory Barrier instruction. */	81	/** Memory Barrier instruction. */
77	static inline void membar(void)	82	static inline void membar(void)
78	{	83	{
79	asm volatile ("membar #Sync\n");	84	asm volatile ("membar #Sync\n");
80	}	85	}
-		86
-		87	#define smc_coherence(a) \
-		88	{ \
-		89	write_barrier(); \
-		90	flush((a)); \
-		91	}
81		92
82	#endif	93	#endif
83		94
84	/** @}	95	/** @}
85	*/	96	*/
86		97

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(root)/trunk/kernel/arch/sparc64/include/barrier.h – Rev 2272 → 3133