WebSVN – HelenOS – Diff – /trunk/kernel/arch/sparc64/include/atomic.h


/*
 * Copyright (c) 2005 Jakub Jermar
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * - Redistributions of source code must retain the above copyright
 *   notice, this list of conditions and the following disclaimer.
 * - Redistributions in binary form must reproduce the above copyright
 *   notice, this list of conditions and the following disclaimer in the
 *   documentation and/or other materials provided with the distribution.
 * - The name of the author may not be used to endorse or promote products
 *   derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
/** @addtogroup sparc64
 * @{
 */
/** @file
 */
 
#ifndef KERN_sparc64_ATOMIC_H_
#define KERN_sparc64_ATOMIC_H_
 
#include <arch/barrier.h>
#include <arch/types.h>
 
/** Atomic add operation.
 *
 * Use atomic compare and swap operation to atomically add signed value.
 *
 * @param val Atomic variable.
 * @param i Signed value to be added.
 *
 * @return Value of the atomic variable as it existed before addition.
 */
static inline long atomic_add(atomic_t *val, int i)
{
    uint64_t a, b;
 
    do {
        volatile uintptr_t x = (uint64_t) &val->count;
 
        a = *((uint64_t *) x);
        b = a + i;
        asm volatile ("casx %0, %2, %1\n" : "+m" (*((uint64_t *)x)), "+r" (b) : "r" (a));
    } while (a != b);
 
    return a;
}
 
static inline long atomic_preinc(atomic_t *val)
{
    return atomic_add(val, 1) + 1;
}
 
static inline long atomic_postinc(atomic_t *val)
{
    return atomic_add(val, 1);
}
 
static inline long atomic_predec(atomic_t *val)
{
    return atomic_add(val, -1) - 1;
}
 
static inline long atomic_postdec(atomic_t *val)
{
    return atomic_add(val, -1);
}
 
static inline void atomic_inc(atomic_t *val)
{
    (void) atomic_add(val, 1);
}
 
static inline void atomic_dec(atomic_t *val)
{
    (void) atomic_add(val, -1);
}
 
static inline long test_and_set(atomic_t *val)
{
    uint64_t v = 1;
    volatile uintptr_t x = (uint64_t) &val->count;
 
    asm volatile ("casx %0, %2, %1\n" : "+m" (*((uint64_t *) x)), "+r" (v) : "r" (0));
 
    return v;
}
 
static inline void atomic_lock_arch(atomic_t *val)
{
    uint64_t tmp1 = 1;
    uint64_t tmp2 = 0;
 
    volatile uintptr_t x = (uint64_t) &val->count;
 
    asm volatile (
    "0:\n"
        "casx %0, %3, %1\n"
        "brz %1, 2f\n"
        "nop\n"
    "1:\n"
        "ldx %0, %2\n"
        "brz %2, 0b\n"
        "nop\n"
        "ba 1b\n"
        "nop\n"
    "2:\n"
        : "+m" (*((uint64_t *) x)), "+r" (tmp1), "+r" (tmp2) : "r" (0)
    );
   
    /*
     * Prevent critical section code from bleeding out this way up.
     */
    CS_ENTER_BARRIER();
}
 
#endif
 
/** @}
 */
 

Rev 2089	Rev 2129
1	/*	1	/*
2	* Copyright (c) 2005 Jakub Jermar	2	* Copyright (c) 2005 Jakub Jermar
3	* All rights reserved.	3	* All rights reserved.
4	*	4	*
5	* Redistribution and use in source and binary forms, with or without	5	* Redistribution and use in source and binary forms, with or without
6	* modification, are permitted provided that the following conditions	6	* modification, are permitted provided that the following conditions
7	* are met:	7	* are met:
8	*	8	*
9	* - Redistributions of source code must retain the above copyright	9	* - Redistributions of source code must retain the above copyright
10	* notice, this list of conditions and the following disclaimer.	10	* notice, this list of conditions and the following disclaimer.
11	* - Redistributions in binary form must reproduce the above copyright	11	* - Redistributions in binary form must reproduce the above copyright
12	* notice, this list of conditions and the following disclaimer in the	12	* notice, this list of conditions and the following disclaimer in the
13	* documentation and/or other materials provided with the distribution.	13	* documentation and/or other materials provided with the distribution.
14	* - The name of the author may not be used to endorse or promote products	14	* - The name of the author may not be used to endorse or promote products
15	* derived from this software without specific prior written permission.	15	* derived from this software without specific prior written permission.
16	*	16	*
17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27	*/	27	*/
28		28
29	/** @addtogroup sparc64	29	/** @addtogroup sparc64
30	* @{	30	* @{
31	*/	31	*/
32	/** @file	32	/** @file
33	*/	33	*/
34		34
35	#ifndef KERN_sparc64_ATOMIC_H_	35	#ifndef KERN_sparc64_ATOMIC_H_
36	#define KERN_sparc64_ATOMIC_H_	36	#define KERN_sparc64_ATOMIC_H_
37		37
38	#include <arch/barrier.h>	38	#include <arch/barrier.h>
39	#include <arch/types.h>	39	#include <arch/types.h>
40		40
41	/** Atomic add operation.	41	/** Atomic add operation.
42	*	42	*
43	* Use atomic compare and swap operation to atomically add signed value.	43	* Use atomic compare and swap operation to atomically add signed value.
44	*	44	*
45	* @param val Atomic variable.	45	* @param val Atomic variable.
46	* @param i Signed value to be added.	46	* @param i Signed value to be added.
47	*	47	*
48	* @return Value of the atomic variable as it existed before addition.	48	* @return Value of the atomic variable as it existed before addition.
49	*/	49	*/
50	static inline long atomic_add(atomic_t *val, int i)	50	static inline long atomic_add(atomic_t *val, int i)
51	{	51	{
52	uint64_t a, b;	52	uint64_t a, b;
53		53
54	do {	54	do {
55	volatile uintptr_t x = (uint64_t) &val->count;	55	volatile uintptr_t x = (uint64_t) &val->count;
56		56
57	a = ((uint64_t ) x);	57	a = ((uint64_t ) x);
58	b = a + i;	58	b = a + i;
59	asm volatile ("casx %0, %2, %1\n" : "+m" (((uint64_t )x)), "+r" (b) : "r" (a));	59	asm volatile ("casx %0, %2, %1\n" : "+m" (((uint64_t )x)), "+r" (b) : "r" (a));
60	} while (a != b);	60	} while (a != b);
61		61
62	return a;	62	return a;
63	}	63	}
64		64
65	static inline long atomic_preinc(atomic_t *val)	65	static inline long atomic_preinc(atomic_t *val)
66	{	66	{
67	return atomic_add(val, 1) + 1;	67	return atomic_add(val, 1) + 1;
68	}	68	}
69		69
70	static inline long atomic_postinc(atomic_t *val)	70	static inline long atomic_postinc(atomic_t *val)
71	{	71	{
72	return atomic_add(val, 1);	72	return atomic_add(val, 1);
73	}	73	}
74		74
75	static inline long atomic_predec(atomic_t *val)	75	static inline long atomic_predec(atomic_t *val)
76	{	76	{
77	return atomic_add(val, -1) - 1;	77	return atomic_add(val, -1) - 1;
78	}	78	}
79		79
80	static inline long atomic_postdec(atomic_t *val)	80	static inline long atomic_postdec(atomic_t *val)
81	{	81	{
82	return atomic_add(val, -1);	82	return atomic_add(val, -1);
83	}	83	}
84		84
85	static inline void atomic_inc(atomic_t *val)	85	static inline void atomic_inc(atomic_t *val)
86	{	86	{
87	(void) atomic_add(val, 1);	87	(void) atomic_add(val, 1);
88	}	88	}
89		89
90	static inline void atomic_dec(atomic_t *val)	90	static inline void atomic_dec(atomic_t *val)
91	{	91	{
92	(void) atomic_add(val, -1);	92	(void) atomic_add(val, -1);
93	}	93	}
94		94
95	static inline long test_and_set(atomic_t *val)	95	static inline long test_and_set(atomic_t *val)
96	{	96	{
97	uint64_t v = 1;	97	uint64_t v = 1;
98	volatile uintptr_t x = (uint64_t) &val->count;	98	volatile uintptr_t x = (uint64_t) &val->count;
99		99
100	asm volatile ("casx %0, %2, %1\n" : "+m" (((uint64_t ) x)), "+r" (v) : "r" (0));	100	asm volatile ("casx %0, %2, %1\n" : "+m" (((uint64_t ) x)), "+r" (v) : "r" (0));
101		101
102	return v;	102	return v;
103	}	103	}
104		104
105	static inline void atomic_lock_arch(atomic_t *val)	105	static inline void atomic_lock_arch(atomic_t *val)
106	{	106	{
107	uint64_t tmp1 = 1;	107	uint64_t tmp1 = 1;
108	uint64_t tmp2;	108	uint64_t tmp2 = 0;
109		109
110	volatile uintptr_t x = (uint64_t) &val->count;	110	volatile uintptr_t x = (uint64_t) &val->count;
111		111
112	asm volatile (	112	asm volatile (
113	"0:\n"	113	"0:\n"
114	"casx %0, %3, %1\n"	114	"casx %0, %3, %1\n"
115	"brz %1, 2f\n"	115	"brz %1, 2f\n"
116	"nop\n"	116	"nop\n"
117	"1:\n"	117	"1:\n"
118	"ldx %0, %2\n"	118	"ldx %0, %2\n"
119	"brz %2, 0b\n"	119	"brz %2, 0b\n"
120	"nop\n"	120	"nop\n"
121	"ba 1b\n"	121	"ba 1b\n"
122	"nop\n"	122	"nop\n"
123	"2:\n"	123	"2:\n"
124	: "+m" (((uint64_t ) x)), "+r" (tmp1), "+r" (tmp2) : "r" (0)	124	: "+m" (((uint64_t ) x)), "+r" (tmp1), "+r" (tmp2) : "r" (0)
125	);	125	);
126		126
127	/*	127	/*
128	* Prevent critical section code from bleeding out this way up.	128	* Prevent critical section code from bleeding out this way up.
129	*/	129	*/
130	CS_ENTER_BARRIER();	130	CS_ENTER_BARRIER();
131	}	131	}
132		132
133	#endif	133	#endif
134		134
135	/** @}	135	/** @}
136	*/	136	*/
137		137

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(root)/trunk/kernel/arch/sparc64/include/atomic.h – Rev 2089 → 2129