WebSVN – HelenOS – Diff – /trunk/kernel/arch/sparc64/include/atomic.h


/*
 * Copyright (c) 2005 Jakub Jermar
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * - Redistributions of source code must retain the above copyright
 *   notice, this list of conditions and the following disclaimer.
 * - Redistributions in binary form must reproduce the above copyright
 *   notice, this list of conditions and the following disclaimer in the
 *   documentation and/or other materials provided with the distribution.
 * - The name of the author may not be used to endorse or promote products
 *   derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
/** @addtogroup sparc64
 * @{
 */
/** @file
 */
 
#ifndef KERN_sparc64_ATOMIC_H_
#define KERN_sparc64_ATOMIC_H_
 
#include <arch/barrier.h>
#include <arch/types.h>
 
 
/** Atomic add operation.
 *
 * Use atomic compare and swap operation to atomically add signed value.
 *
 * @param val Atomic variable.
 * @param i Signed value to be added.
 *
 * @return Value of the atomic variable as it existed before addition.
 */
static inline long atomic_add(atomic_t *val, int i)
{
    uint64_t a, b;
 
    do {
        volatile uintptr_t x = (uint64_t) &val->count;
 
        a = *((uint64_t *) x);
        b = a + i;
        asm volatile ("casx %0, %2, %1\n" : "+m" (*((uint64_t *)x)), "+r" (b) : "r" (a));
    } while (a != b);
 
    return a;
}
 
static inline long atomic_preinc(atomic_t *val)
{
    return atomic_add(val, 1) + 1;
}
 
static inline long atomic_postinc(atomic_t *val)
{
    return atomic_add(val, 1);
}
 
static inline long atomic_predec(atomic_t *val)
{
    return atomic_add(val, -1) - 1;
}
 
static inline long atomic_postdec(atomic_t *val)
{
    return atomic_add(val, -1);
}
 
static inline void atomic_inc(atomic_t *val)
{
    (void) atomic_add(val, 1);
}
 
static inline void atomic_dec(atomic_t *val)
{
    (void) atomic_add(val, -1);
}
 
static inline long test_and_set(atomic_t *val)
{
    uint64_t v = 1;
    volatile uintptr_t x = (uint64_t) &val->count;
 
    asm volatile ("casx %0, %2, %1\n" : "+m" (*((uint64_t *) x)), "+r" (v) : "r" (0));
 
    return v;
}
 
static inline void atomic_lock_arch(atomic_t *val)
{
    uint64_t tmp1 = 1;
    uint64_t tmp2;
 
    volatile uintptr_t x = (uint64_t) &val->count;
 
    asm volatile (
    "0:\n"
        "casx %0, %3, %1\n"
        "brz %1, 2f\n"
        "nop\n"
    "1:\n"
        "ldx %0, %2\n"
        "brz %2, 0b\n"
        "nop\n"
        "ba 1b\n"
        "nop\n"
    "2:\n"
        : "+m" (*((uint64_t *) x)), "+r" (tmp1), "+r" (tmp2) : "r" (0)
    );
   
    /*
     * Prevent critical section code from bleeding out this way up.
     */
    CS_ENTER_BARRIER();
}
 
#endif
 
/** @}
 */
 

Rev 2082	Rev 2089
1	/*	1	/*
2	* Copyright (c) 2005 Jakub Jermar	2	* Copyright (c) 2005 Jakub Jermar
3	* All rights reserved.	3	* All rights reserved.
4	*	4	*
5	* Redistribution and use in source and binary forms, with or without	5	* Redistribution and use in source and binary forms, with or without
6	* modification, are permitted provided that the following conditions	6	* modification, are permitted provided that the following conditions
7	* are met:	7	* are met:
8	*	8	*
9	* - Redistributions of source code must retain the above copyright	9	* - Redistributions of source code must retain the above copyright
10	* notice, this list of conditions and the following disclaimer.	10	* notice, this list of conditions and the following disclaimer.
11	* - Redistributions in binary form must reproduce the above copyright	11	* - Redistributions in binary form must reproduce the above copyright
12	* notice, this list of conditions and the following disclaimer in the	12	* notice, this list of conditions and the following disclaimer in the
13	* documentation and/or other materials provided with the distribution.	13	* documentation and/or other materials provided with the distribution.
14	* - The name of the author may not be used to endorse or promote products	14	* - The name of the author may not be used to endorse or promote products
15	* derived from this software without specific prior written permission.	15	* derived from this software without specific prior written permission.
16	*	16	*
17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27	*/	27	*/
28		28
29	/** @addtogroup sparc64	29	/** @addtogroup sparc64
30	* @{	30	* @{
31	*/	31	*/
32	/** @file	32	/** @file
33	*/	33	*/
34		34
35	#ifndef KERN_sparc64_ATOMIC_H_	35	#ifndef KERN_sparc64_ATOMIC_H_
36	#define KERN_sparc64_ATOMIC_H_	36	#define KERN_sparc64_ATOMIC_H_
37		37
38	#include <arch/barrier.h>	38	#include <arch/barrier.h>
39	#include <arch/types.h>	39	#include <arch/types.h>
40	#include <typedefs.h>	-
41		40
42	/** Atomic add operation.	41	/** Atomic add operation.
43	*	42	*
44	* Use atomic compare and swap operation to atomically add signed value.	43	* Use atomic compare and swap operation to atomically add signed value.
45	*	44	*
46	* @param val Atomic variable.	45	* @param val Atomic variable.
47	* @param i Signed value to be added.	46	* @param i Signed value to be added.
48	*	47	*
49	* @return Value of the atomic variable as it existed before addition.	48	* @return Value of the atomic variable as it existed before addition.
50	*/	49	*/
51	static inline long atomic_add(atomic_t *val, int i)	50	static inline long atomic_add(atomic_t *val, int i)
52	{	51	{
53	uint64_t a, b;	52	uint64_t a, b;
54		53
55	do {	54	do {
56	volatile uintptr_t x = (uint64_t) &val->count;	55	volatile uintptr_t x = (uint64_t) &val->count;
57		56
58	a = ((uint64_t ) x);	57	a = ((uint64_t ) x);
59	b = a + i;	58	b = a + i;
60	asm volatile ("casx %0, %2, %1\n" : "+m" (((uint64_t )x)), "+r" (b) : "r" (a));	59	asm volatile ("casx %0, %2, %1\n" : "+m" (((uint64_t )x)), "+r" (b) : "r" (a));
61	} while (a != b);	60	} while (a != b);
62		61
63	return a;	62	return a;
64	}	63	}
65		64
66	static inline long atomic_preinc(atomic_t *val)	65	static inline long atomic_preinc(atomic_t *val)
67	{	66	{
68	return atomic_add(val, 1) + 1;	67	return atomic_add(val, 1) + 1;
69	}	68	}
70		69
71	static inline long atomic_postinc(atomic_t *val)	70	static inline long atomic_postinc(atomic_t *val)
72	{	71	{
73	return atomic_add(val, 1);	72	return atomic_add(val, 1);
74	}	73	}
75		74
76	static inline long atomic_predec(atomic_t *val)	75	static inline long atomic_predec(atomic_t *val)
77	{	76	{
78	return atomic_add(val, -1) - 1;	77	return atomic_add(val, -1) - 1;
79	}	78	}
80		79
81	static inline long atomic_postdec(atomic_t *val)	80	static inline long atomic_postdec(atomic_t *val)
82	{	81	{
83	return atomic_add(val, -1);	82	return atomic_add(val, -1);
84	}	83	}
85		84
86	static inline void atomic_inc(atomic_t *val)	85	static inline void atomic_inc(atomic_t *val)
87	{	86	{
88	(void) atomic_add(val, 1);	87	(void) atomic_add(val, 1);
89	}	88	}
90		89
91	static inline void atomic_dec(atomic_t *val)	90	static inline void atomic_dec(atomic_t *val)
92	{	91	{
93	(void) atomic_add(val, -1);	92	(void) atomic_add(val, -1);
94	}	93	}
95		94
96	static inline long test_and_set(atomic_t *val)	95	static inline long test_and_set(atomic_t *val)
97	{	96	{
98	uint64_t v = 1;	97	uint64_t v = 1;
99	volatile uintptr_t x = (uint64_t) &val->count;	98	volatile uintptr_t x = (uint64_t) &val->count;
100		99
101	asm volatile ("casx %0, %2, %1\n" : "+m" (((uint64_t ) x)), "+r" (v) : "r" (0));	100	asm volatile ("casx %0, %2, %1\n" : "+m" (((uint64_t ) x)), "+r" (v) : "r" (0));
102		101
103	return v;	102	return v;
104	}	103	}
105		104
106	static inline void atomic_lock_arch(atomic_t *val)	105	static inline void atomic_lock_arch(atomic_t *val)
107	{	106	{
108	uint64_t tmp1 = 1;	107	uint64_t tmp1 = 1;
109	uint64_t tmp2;	108	uint64_t tmp2;
110		109
111	volatile uintptr_t x = (uint64_t) &val->count;	110	volatile uintptr_t x = (uint64_t) &val->count;
112		111
113	asm volatile (	112	asm volatile (
114	"0:\n"	113	"0:\n"
115	"casx %0, %3, %1\n"	114	"casx %0, %3, %1\n"
116	"brz %1, 2f\n"	115	"brz %1, 2f\n"
117	"nop\n"	116	"nop\n"
118	"1:\n"	117	"1:\n"
119	"ldx %0, %2\n"	118	"ldx %0, %2\n"
120	"brz %2, 0b\n"	119	"brz %2, 0b\n"
121	"nop\n"	120	"nop\n"
122	"ba 1b\n"	121	"ba 1b\n"
123	"nop\n"	122	"nop\n"
124	"2:\n"	123	"2:\n"
125	: "+m" (((uint64_t ) x)), "+r" (tmp1), "+r" (tmp2) : "r" (0)	124	: "+m" (((uint64_t ) x)), "+r" (tmp1), "+r" (tmp2) : "r" (0)
126	);	125	);
127		126
128	/*	127	/*
129	* Prevent critical section code from bleeding out this way up.	128	* Prevent critical section code from bleeding out this way up.
130	*/	129	*/
131	CS_ENTER_BARRIER();	130	CS_ENTER_BARRIER();
132	}	131	}
133		132
134	#endif	133	#endif
135		134
136	/** @}	135	/** @}
137	*/	136	*/
138		137

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(root)/trunk/kernel/arch/sparc64/include/atomic.h – Rev 2082 → 2089