WebSVN – HelenOS – Diff – /trunk/kernel/arch/sparc64/include/asm.h


/*
 * Copyright (c) 2005 Jakub Jermar
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * - Redistributions of source code must retain the above copyright
 *   notice, this list of conditions and the following disclaimer.
 * - Redistributions in binary form must reproduce the above copyright
 *   notice, this list of conditions and the following disclaimer in the
 *   documentation and/or other materials provided with the distribution.
 * - The name of the author may not be used to endorse or promote products
 *   derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
/** @addtogroup sparc64
 * @{
 */
/** @file
 */
 
#ifndef KERN_sparc64_ASM_H_
#define KERN_sparc64_ASM_H_
 
#include <arch/arch.h>
#include <arch/types.h>
#include <typedefs.h>
#include <align.h>
#include <arch/register.h>
#include <config.h>
#include <arch/stack.h>
 
/** Read Processor State register.
 *
 * @return Value of PSTATE register.
 */
static inline uint64_t pstate_read(void)
{
    uint64_t v;
   
    asm volatile ("rdpr %%pstate, %0\n" : "=r" (v));
   
    return v;
}
 
/** Write Processor State register.
 *
 * @param v New value of PSTATE register.
 */
static inline void pstate_write(uint64_t v)
{
    asm volatile ("wrpr %0, %1, %%pstate\n" : : "r" (v), "i" (0));
}
 
/** Read TICK_compare Register.
 *
 * @return Value of TICK_comapre register.
 */
static inline uint64_t tick_compare_read(void)
{
    uint64_t v;
   
    asm volatile ("rd %%tick_cmpr, %0\n" : "=r" (v));
   
    return v;
}
 
/** Write TICK_compare Register.
 *
 * @param v New value of TICK_comapre register.
 */
static inline void tick_compare_write(uint64_t v)
{
    asm volatile ("wr %0, %1, %%tick_cmpr\n" : : "r" (v), "i" (0));
}
 
/** Read TICK Register.
 *
 * @return Value of TICK register.
 */
static inline uint64_t tick_read(void)
{
    uint64_t v;
   
    asm volatile ("rdpr %%tick, %0\n" : "=r" (v));
   
    return v;
}
 
/** Write TICK Register.
 *
 * @param v New value of TICK register.
 */
static inline void tick_write(uint64_t v)
{
    asm volatile ("wrpr %0, %1, %%tick\n" : : "r" (v), "i" (0));
}
 
/** Read FPRS Register.
 *
 * @return Value of FPRS register.
 */
static inline uint64_t fprs_read(void)
{
    uint64_t v;
   
    asm volatile ("rd %%fprs, %0\n" : "=r" (v));
   
    return v;
}
 
/** Write FPRS Register.
 *
 * @param v New value of FPRS register.
 */
static inline void fprs_write(uint64_t v)
{
    asm volatile ("wr %0, %1, %%fprs\n" : : "r" (v), "i" (0));
}
 
/** Read SOFTINT Register.
 *
 * @return Value of SOFTINT register.
 */
static inline uint64_t softint_read(void)
{
    uint64_t v;
 
    asm volatile ("rd %%softint, %0\n" : "=r" (v));
 
    return v;
}
 
/** Write SOFTINT Register.
 *
 * @param v New value of SOFTINT register.
 */
static inline void softint_write(uint64_t v)
{
    asm volatile ("wr %0, %1, %%softint\n" : : "r" (v), "i" (0));
}
 
/** Write CLEAR_SOFTINT Register.
 *
 * Bits set in CLEAR_SOFTINT register will be cleared in SOFTINT register.
 *
 * @param v New value of CLEAR_SOFTINT register.
 */
static inline void clear_softint_write(uint64_t v)
{
    asm volatile ("wr %0, %1, %%clear_softint\n" : : "r" (v), "i" (0));
}
 
/** Write SET_SOFTINT Register.
 *
 * Bits set in SET_SOFTINT register will be set in SOFTINT register.
 *
 * @param v New value of SET_SOFTINT register.
 */
static inline void set_softint_write(uint64_t v)
{
    asm volatile ("wr %0, %1, %%set_softint\n" : : "r" (v), "i" (0));
}
 
/** Enable interrupts.
 *
 * Enable interrupts and return previous
 * value of IPL.
 *
 * @return Old interrupt priority level.
 */
static inline ipl_t interrupts_enable(void) {
    pstate_reg_t pstate;
    uint64_t value;
   
    value = pstate_read();
    pstate.value = value;
    pstate.ie = true;
    pstate_write(pstate.value);
   
    return (ipl_t) value;
}
 
/** Disable interrupts.
 *
 * Disable interrupts and return previous
 * value of IPL.
 *
 * @return Old interrupt priority level.
 */
static inline ipl_t interrupts_disable(void) {
    pstate_reg_t pstate;
    uint64_t value;
   
    value = pstate_read();
    pstate.value = value;
    pstate.ie = false;
    pstate_write(pstate.value);
   
    return (ipl_t) value;
}
 
/** Restore interrupt priority level.
 *
 * Restore IPL.
 *
 * @param ipl Saved interrupt priority level.
 */
static inline void interrupts_restore(ipl_t ipl) {
    pstate_reg_t pstate;
   
    pstate.value = pstate_read();
    pstate.ie = ((pstate_reg_t) ipl).ie;
    pstate_write(pstate.value);
}
 
/** Return interrupt priority level.
 *
 * Return IPL.
 *
 * @return Current interrupt priority level.
 */
static inline ipl_t interrupts_read(void) {
    return (ipl_t) pstate_read();
}
 
/** Return base address of current stack.
 *
 * Return the base address of the current stack.
 * The stack is assumed to be STACK_SIZE bytes long.
 * The stack must start on page boundary.
 */
static inline uintptr_t get_stack_base(void)
{
    uintptr_t unbiased_sp;
   
    asm volatile ("add %%sp, %1, %0\n" : "=r" (unbiased_sp) : "i" (STACK_BIAS));
   
    return ALIGN_DOWN(unbiased_sp, STACK_SIZE);
}
 
/** Read Version Register.
 *
 * @return Value of VER register.
 */
static inline uint64_t ver_read(void)
{
    uint64_t v;
   
    asm volatile ("rdpr %%ver, %0\n" : "=r" (v));
   
    return v;
}
 
/** Read Trap Program Counter register.
 *
 * @return Current value in TPC.
 */
static inline uint64_t tpc_read(void)
{
    uint64_t v;
   
    asm volatile ("rdpr %%tpc, %0\n" : "=r" (v));
   
    return v;
}
 
/** Read Trap Level register.
 *
 * @return Current value in TL.
 */
static inline uint64_t tl_read(void)
{
    uint64_t v;
   
    asm volatile ("rdpr %%tl, %0\n" : "=r" (v));
   
    return v;
}
 
/** Read Trap Base Address register.
 *
 * @return Current value in TBA.
 */
static inline uint64_t tba_read(void)
{
    uint64_t v;
   
    asm volatile ("rdpr %%tba, %0\n" : "=r" (v));
   
    return v;
}
 
/** Write Trap Base Address register.
 *
 * @param v New value of TBA.
 */
static inline void tba_write(uint64_t v)
{
    asm volatile ("wrpr %0, %1, %%tba\n" : : "r" (v), "i" (0));
}
 
/** Load uint64_t from alternate space.
 *
 * @param asi ASI determining the alternate space.
 * @param va Virtual address within the ASI.
 *
 * @return Value read from the virtual address in the specified address space.
 */
static inline uint64_t asi_u64_read(asi_t asi, uintptr_t va)
{
    uint64_t v;
   
    asm volatile ("ldxa [%1] %2, %0\n" : "=r" (v) : "r" (va), "i" ((unsigned) asi));
   
    return v;
}
 
/** Store uint64_t to alternate space.
 *
 * @param asi ASI determining the alternate space.
 * @param va Virtual address within the ASI.
 * @param v Value to be written.
 */
static inline void asi_u64_write(asi_t asi, uintptr_t va, uint64_t v)
{
    asm volatile ("stxa %0, [%1] %2\n" : :  "r" (v), "r" (va), "i" ((unsigned) asi) : "memory");
}
 
/** Flush all valid register windows to memory. */
static inline void flushw(void)
{
    asm volatile ("flushw\n");
}
 
/** Switch to nucleus by setting TL to 1. */
static inline void nucleus_enter(void)
{
    asm volatile ("wrpr %g0, 1, %tl\n");
}
 
/** Switch from nucleus by setting TL to 0. */
static inline void nucleus_leave(void)
{
    asm volatile ("wrpr %g0, %g0, %tl\n");
}
 
/** Read UPA_CONFIG register.
 *
 * @return Value of the UPA_CONFIG register.
 */
static inline uint64_t upa_config_read(void)
{
    return asi_u64_read(ASI_UPA_CONFIG, 0);
}
 
extern void cpu_halt(void);
extern void cpu_sleep(void);
extern void asm_delay_loop(const uint32_t usec);
 
extern uint64_t read_from_ag_g7(void);
extern void write_to_ag_g6(uint64_t val);
extern void write_to_ag_g7(uint64_t val);
extern void write_to_ig_g6(uint64_t val);
 
extern void switch_to_userspace(uint64_t pc, uint64_t sp, uint64_t uarg);
 
#endif
 
/** @}
 */
 

Subversion Repositories HelenOS

(root)/trunk/kernel/arch/sparc64/include/asm.h – Rev 2089 → 3071

Rev 2089		Rev 3071
1	/*	1	/*
2	* Copyright (c) 2005 Jakub Jermar	2	* Copyright (c) 2005 Jakub Jermar
3	* All rights reserved.	3	* All rights reserved.
4	*	4	*
5	* Redistribution and use in source and binary forms, with or without	5	* Redistribution and use in source and binary forms, with or without
6	* modification, are permitted provided that the following conditions	6	* modification, are permitted provided that the following conditions
7	* are met:	7	* are met:
8	*	8	*
9	* - Redistributions of source code must retain the above copyright	9	* - Redistributions of source code must retain the above copyright
10	* notice, this list of conditions and the following disclaimer.	10	* notice, this list of conditions and the following disclaimer.
11	* - Redistributions in binary form must reproduce the above copyright	11	* - Redistributions in binary form must reproduce the above copyright
12	* notice, this list of conditions and the following disclaimer in the	12	* notice, this list of conditions and the following disclaimer in the
13	* documentation and/or other materials provided with the distribution.	13	* documentation and/or other materials provided with the distribution.
14	* - The name of the author may not be used to endorse or promote products	14	* - The name of the author may not be used to endorse or promote products
15	* derived from this software without specific prior written permission.	15	* derived from this software without specific prior written permission.
16	*	16	*
17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27	*/	27	*/
28		28
29	/** @addtogroup sparc64	29	/** @addtogroup sparc64
30	* @{	30	* @{
31	*/	31	*/
32	/** @file	32	/** @file
33	*/	33	*/
34		34
35	#ifndef KERN_sparc64_ASM_H_	35	#ifndef KERN_sparc64_ASM_H_
36	#define KERN_sparc64_ASM_H_	36	#define KERN_sparc64_ASM_H_
37		37
38	#include <arch/arch.h>	38	#include <arch/arch.h>
39	#include <arch/types.h>	39	#include <arch/types.h>
-		40	#include <typedefs.h>
40	#include <align.h>	41	#include <align.h>
41	#include <arch/register.h>	42	#include <arch/register.h>
42	#include <config.h>	43	#include <config.h>
43	#include <arch/stack.h>	44	#include <arch/stack.h>
44		45
45	/** Read Processor State register.	46	/** Read Processor State register.
46	*	47	*
47	* @return Value of PSTATE register.	48	* @return Value of PSTATE register.
48	*/	49	*/
49	static inline uint64_t pstate_read(void)	50	static inline uint64_t pstate_read(void)
50	{	51	{
51	uint64_t v;	52	uint64_t v;
52		53
53	asm volatile ("rdpr %%pstate, %0\n" : "=r" (v));	54	asm volatile ("rdpr %%pstate, %0\n" : "=r" (v));
54		55
55	return v;	56	return v;
56	}	57	}
57		58
58	/** Write Processor State register.	59	/** Write Processor State register.
59	*	60	*
60	* @param v New value of PSTATE register.	61	* @param v New value of PSTATE register.
61	*/	62	*/
62	static inline void pstate_write(uint64_t v)	63	static inline void pstate_write(uint64_t v)
63	{	64	{
64	asm volatile ("wrpr %0, %1, %%pstate\n" : : "r" (v), "i" (0));	65	asm volatile ("wrpr %0, %1, %%pstate\n" : : "r" (v), "i" (0));
65	}	66	}
66		67
67	/** Read TICK_compare Register.	68	/** Read TICK_compare Register.
68	*	69	*
69	* @return Value of TICK_comapre register.	70	* @return Value of TICK_comapre register.
70	*/	71	*/
71	static inline uint64_t tick_compare_read(void)	72	static inline uint64_t tick_compare_read(void)
72	{	73	{
73	uint64_t v;	74	uint64_t v;
74		75
75	asm volatile ("rd %%tick_cmpr, %0\n" : "=r" (v));	76	asm volatile ("rd %%tick_cmpr, %0\n" : "=r" (v));
76		77
77	return v;	78	return v;
78	}	79	}
79		80
80	/** Write TICK_compare Register.	81	/** Write TICK_compare Register.
81	*	82	*
82	* @param v New value of TICK_comapre register.	83	* @param v New value of TICK_comapre register.
83	*/	84	*/
84	static inline void tick_compare_write(uint64_t v)	85	static inline void tick_compare_write(uint64_t v)
85	{	86	{
86	asm volatile ("wr %0, %1, %%tick_cmpr\n" : : "r" (v), "i" (0));	87	asm volatile ("wr %0, %1, %%tick_cmpr\n" : : "r" (v), "i" (0));
87	}	88	}
88		89
89	/** Read TICK Register.	90	/** Read TICK Register.
90	*	91	*
91	* @return Value of TICK register.	92	* @return Value of TICK register.
92	*/	93	*/
93	static inline uint64_t tick_read(void)	94	static inline uint64_t tick_read(void)
94	{	95	{
95	uint64_t v;	96	uint64_t v;
96		97
97	asm volatile ("rdpr %%tick, %0\n" : "=r" (v));	98	asm volatile ("rdpr %%tick, %0\n" : "=r" (v));
98		99
99	return v;	100	return v;
100	}	101	}
101		102
102	/** Write TICK Register.	103	/** Write TICK Register.
103	*	104	*
104	* @param v New value of TICK register.	105	* @param v New value of TICK register.
105	*/	106	*/
106	static inline void tick_write(uint64_t v)	107	static inline void tick_write(uint64_t v)
107	{	108	{
108	asm volatile ("wrpr %0, %1, %%tick\n" : : "r" (v), "i" (0));	109	asm volatile ("wrpr %0, %1, %%tick\n" : : "r" (v), "i" (0));
109	}	110	}
110		111
111	/** Read FPRS Register.	112	/** Read FPRS Register.
112	*	113	*
113	* @return Value of FPRS register.	114	* @return Value of FPRS register.
114	*/	115	*/
115	static inline uint64_t fprs_read(void)	116	static inline uint64_t fprs_read(void)
116	{	117	{
117	uint64_t v;	118	uint64_t v;
118		119
119	asm volatile ("rd %%fprs, %0\n" : "=r" (v));	120	asm volatile ("rd %%fprs, %0\n" : "=r" (v));
120		121
121	return v;	122	return v;
122	}	123	}
123		124
124	/** Write FPRS Register.	125	/** Write FPRS Register.
125	*	126	*
126	* @param v New value of FPRS register.	127	* @param v New value of FPRS register.
127	*/	128	*/
128	static inline void fprs_write(uint64_t v)	129	static inline void fprs_write(uint64_t v)
129	{	130	{
130	asm volatile ("wr %0, %1, %%fprs\n" : : "r" (v), "i" (0));	131	asm volatile ("wr %0, %1, %%fprs\n" : : "r" (v), "i" (0));
131	}	132	}
132		133
133	/** Read SOFTINT Register.	134	/** Read SOFTINT Register.
134	*	135	*
135	* @return Value of SOFTINT register.	136	* @return Value of SOFTINT register.
136	*/	137	*/
137	static inline uint64_t softint_read(void)	138	static inline uint64_t softint_read(void)
138	{	139	{
139	uint64_t v;	140	uint64_t v;
140		141
141	asm volatile ("rd %%softint, %0\n" : "=r" (v));	142	asm volatile ("rd %%softint, %0\n" : "=r" (v));
142		143
143	return v;	144	return v;
144	}	145	}
145		146
146	/** Write SOFTINT Register.	147	/** Write SOFTINT Register.
147	*	148	*
148	* @param v New value of SOFTINT register.	149	* @param v New value of SOFTINT register.
149	*/	150	*/
150	static inline void softint_write(uint64_t v)	151	static inline void softint_write(uint64_t v)
151	{	152	{
152	asm volatile ("wr %0, %1, %%softint\n" : : "r" (v), "i" (0));	153	asm volatile ("wr %0, %1, %%softint\n" : : "r" (v), "i" (0));
153	}	154	}
154		155
155	/** Write CLEAR_SOFTINT Register.	156	/** Write CLEAR_SOFTINT Register.
156	*	157	*
157	* Bits set in CLEAR_SOFTINT register will be cleared in SOFTINT register.	158	* Bits set in CLEAR_SOFTINT register will be cleared in SOFTINT register.
158	*	159	*
159	* @param v New value of CLEAR_SOFTINT register.	160	* @param v New value of CLEAR_SOFTINT register.
160	*/	161	*/
161	static inline void clear_softint_write(uint64_t v)	162	static inline void clear_softint_write(uint64_t v)
162	{	163	{
163	asm volatile ("wr %0, %1, %%clear_softint\n" : : "r" (v), "i" (0));	164	asm volatile ("wr %0, %1, %%clear_softint\n" : : "r" (v), "i" (0));
164	}	165	}
165		166
166	/** Write SET_SOFTINT Register.	167	/** Write SET_SOFTINT Register.
167	*	168	*
168	* Bits set in SET_SOFTINT register will be set in SOFTINT register.	169	* Bits set in SET_SOFTINT register will be set in SOFTINT register.
169	*	170	*
170	* @param v New value of SET_SOFTINT register.	171	* @param v New value of SET_SOFTINT register.
171	*/	172	*/
172	static inline void set_softint_write(uint64_t v)	173	static inline void set_softint_write(uint64_t v)
173	{	174	{
174	asm volatile ("wr %0, %1, %%set_softint\n" : : "r" (v), "i" (0));	175	asm volatile ("wr %0, %1, %%set_softint\n" : : "r" (v), "i" (0));
175	}	176	}
176		177
177	/** Enable interrupts.	178	/** Enable interrupts.
178	*	179	*
179	* Enable interrupts and return previous	180	* Enable interrupts and return previous
180	* value of IPL.	181	* value of IPL.
181	*	182	*
182	* @return Old interrupt priority level.	183	* @return Old interrupt priority level.
183	*/	184	*/
184	static inline ipl_t interrupts_enable(void) {	185	static inline ipl_t interrupts_enable(void) {
185	pstate_reg_t pstate;	186	pstate_reg_t pstate;
186	uint64_t value;	187	uint64_t value;
187		188
188	value = pstate_read();	189	value = pstate_read();
189	pstate.value = value;	190	pstate.value = value;
190	pstate.ie = true;	191	pstate.ie = true;
191	pstate_write(pstate.value);	192	pstate_write(pstate.value);
192		193
193	return (ipl_t) value;	194	return (ipl_t) value;
194	}	195	}
195		196
196	/** Disable interrupts.	197	/** Disable interrupts.
197	*	198	*
198	* Disable interrupts and return previous	199	* Disable interrupts and return previous
199	* value of IPL.	200	* value of IPL.
200	*	201	*
201	* @return Old interrupt priority level.	202	* @return Old interrupt priority level.
202	*/	203	*/
203	static inline ipl_t interrupts_disable(void) {	204	static inline ipl_t interrupts_disable(void) {
204	pstate_reg_t pstate;	205	pstate_reg_t pstate;
205	uint64_t value;	206	uint64_t value;
206		207
207	value = pstate_read();	208	value = pstate_read();
208	pstate.value = value;	209	pstate.value = value;
209	pstate.ie = false;	210	pstate.ie = false;
210	pstate_write(pstate.value);	211	pstate_write(pstate.value);
211		212
212	return (ipl_t) value;	213	return (ipl_t) value;
213	}	214	}
214		215
215	/** Restore interrupt priority level.	216	/** Restore interrupt priority level.
216	*	217	*
217	* Restore IPL.	218	* Restore IPL.
218	*	219	*
219	* @param ipl Saved interrupt priority level.	220	* @param ipl Saved interrupt priority level.
220	*/	221	*/
221	static inline void interrupts_restore(ipl_t ipl) {	222	static inline void interrupts_restore(ipl_t ipl) {
222	pstate_reg_t pstate;	223	pstate_reg_t pstate;
223		224
224	pstate.value = pstate_read();	225	pstate.value = pstate_read();
225	pstate.ie = ((pstate_reg_t) ipl).ie;	226	pstate.ie = ((pstate_reg_t) ipl).ie;
226	pstate_write(pstate.value);	227	pstate_write(pstate.value);
227	}	228	}
228		229
229	/** Return interrupt priority level.	230	/** Return interrupt priority level.
230	*	231	*
231	* Return IPL.	232	* Return IPL.
232	*	233	*
233	* @return Current interrupt priority level.	234	* @return Current interrupt priority level.
234	*/	235	*/
235	static inline ipl_t interrupts_read(void) {	236	static inline ipl_t interrupts_read(void) {
236	return (ipl_t) pstate_read();	237	return (ipl_t) pstate_read();
237	}	238	}
238		239
239	/** Return base address of current stack.	240	/** Return base address of current stack.
240	*	241	*
241	* Return the base address of the current stack.	242	* Return the base address of the current stack.
242	* The stack is assumed to be STACK_SIZE bytes long.	243	* The stack is assumed to be STACK_SIZE bytes long.
243	* The stack must start on page boundary.	244	* The stack must start on page boundary.
244	*/	245	*/
245	static inline uintptr_t get_stack_base(void)	246	static inline uintptr_t get_stack_base(void)
246	{	247	{
247	uintptr_t unbiased_sp;	248	uintptr_t unbiased_sp;
248		249
249	asm volatile ("add %%sp, %1, %0\n" : "=r" (unbiased_sp) : "i" (STACK_BIAS));	250	asm volatile ("add %%sp, %1, %0\n" : "=r" (unbiased_sp) : "i" (STACK_BIAS));
250		251
251	return ALIGN_DOWN(unbiased_sp, STACK_SIZE);	252	return ALIGN_DOWN(unbiased_sp, STACK_SIZE);
252	}	253	}
253		254
254	/** Read Version Register.	255	/** Read Version Register.
255	*	256	*
256	* @return Value of VER register.	257	* @return Value of VER register.
257	*/	258	*/
258	static inline uint64_t ver_read(void)	259	static inline uint64_t ver_read(void)
259	{	260	{
260	uint64_t v;	261	uint64_t v;
261		262
262	asm volatile ("rdpr %%ver, %0\n" : "=r" (v));	263	asm volatile ("rdpr %%ver, %0\n" : "=r" (v));
263		264
264	return v;	265	return v;
265	}	266	}
266		267
267	/** Read Trap Program Counter register.	268	/** Read Trap Program Counter register.
268	*	269	*
269	* @return Current value in TPC.	270	* @return Current value in TPC.
270	*/	271	*/
271	static inline uint64_t tpc_read(void)	272	static inline uint64_t tpc_read(void)
272	{	273	{
273	uint64_t v;	274	uint64_t v;
274		275
275	asm volatile ("rdpr %%tpc, %0\n" : "=r" (v));	276	asm volatile ("rdpr %%tpc, %0\n" : "=r" (v));
276		277
277	return v;	278	return v;
278	}	279	}
279		280
280	/** Read Trap Level register.	281	/** Read Trap Level register.
281	*	282	*
282	* @return Current value in TL.	283	* @return Current value in TL.
283	*/	284	*/
284	static inline uint64_t tl_read(void)	285	static inline uint64_t tl_read(void)
285	{	286	{
286	uint64_t v;	287	uint64_t v;
287		288
288	asm volatile ("rdpr %%tl, %0\n" : "=r" (v));	289	asm volatile ("rdpr %%tl, %0\n" : "=r" (v));
289		290
290	return v;	291	return v;
291	}	292	}
292		293
293	/** Read Trap Base Address register.	294	/** Read Trap Base Address register.
294	*	295	*
295	* @return Current value in TBA.	296	* @return Current value in TBA.
296	*/	297	*/
297	static inline uint64_t tba_read(void)	298	static inline uint64_t tba_read(void)
298	{	299	{
299	uint64_t v;	300	uint64_t v;
300		301
301	asm volatile ("rdpr %%tba, %0\n" : "=r" (v));	302	asm volatile ("rdpr %%tba, %0\n" : "=r" (v));
302		303
303	return v;	304	return v;
304	}	305	}
305		306
306	/** Write Trap Base Address register.	307	/** Write Trap Base Address register.
307	*	308	*
308	* @param v New value of TBA.	309	* @param v New value of TBA.
309	*/	310	*/
310	static inline void tba_write(uint64_t v)	311	static inline void tba_write(uint64_t v)
311	{	312	{
312	asm volatile ("wrpr %0, %1, %%tba\n" : : "r" (v), "i" (0));	313	asm volatile ("wrpr %0, %1, %%tba\n" : : "r" (v), "i" (0));
313	}	314	}
314		315
315	/** Load uint64_t from alternate space.	316	/** Load uint64_t from alternate space.
316	*	317	*
317	* @param asi ASI determining the alternate space.	318	* @param asi ASI determining the alternate space.
318	* @param va Virtual address within the ASI.	319	* @param va Virtual address within the ASI.
319	*	320	*
320	* @return Value read from the virtual address in the specified address space.	321	* @return Value read from the virtual address in the specified address space.
321	*/	322	*/
322	static inline uint64_t asi_u64_read(asi_t asi, uintptr_t va)	323	static inline uint64_t asi_u64_read(asi_t asi, uintptr_t va)
323	{	324	{
324	uint64_t v;	325	uint64_t v;
325		326
326	asm volatile ("ldxa [%1] %2, %0\n" : "=r" (v) : "r" (va), "i" ((unsigned) asi));	327	asm volatile ("ldxa [%1] %2, %0\n" : "=r" (v) : "r" (va), "i" ((unsigned) asi));
327		328
328	return v;	329	return v;
329	}	330	}
330		331
331	/** Store uint64_t to alternate space.	332	/** Store uint64_t to alternate space.
332	*	333	*
333	* @param asi ASI determining the alternate space.	334	* @param asi ASI determining the alternate space.
334	* @param va Virtual address within the ASI.	335	* @param va Virtual address within the ASI.
335	* @param v Value to be written.	336	* @param v Value to be written.
336	*/	337	*/
337	static inline void asi_u64_write(asi_t asi, uintptr_t va, uint64_t v)	338	static inline void asi_u64_write(asi_t asi, uintptr_t va, uint64_t v)
338	{	339	{
339	asm volatile ("stxa %0, [%1] %2\n" : : "r" (v), "r" (va), "i" ((unsigned) asi) : "memory");	340	asm volatile ("stxa %0, [%1] %2\n" : : "r" (v), "r" (va), "i" ((unsigned) asi) : "memory");
340	}	341	}
341		342
342	/** Flush all valid register windows to memory. */	343	/** Flush all valid register windows to memory. */
343	static inline void flushw(void)	344	static inline void flushw(void)
344	{	345	{
345	asm volatile ("flushw\n");	346	asm volatile ("flushw\n");
346	}	347	}
347		348
348	/** Switch to nucleus by setting TL to 1. */	349	/** Switch to nucleus by setting TL to 1. */
349	static inline void nucleus_enter(void)	350	static inline void nucleus_enter(void)
350	{	351	{
351	asm volatile ("wrpr %g0, 1, %tl\n");	352	asm volatile ("wrpr %g0, 1, %tl\n");
352	}	353	}
353		354
354	/** Switch from nucleus by setting TL to 0. */	355	/** Switch from nucleus by setting TL to 0. */
355	static inline void nucleus_leave(void)	356	static inline void nucleus_leave(void)
356	{	357	{
357	asm volatile ("wrpr %g0, %g0, %tl\n");	358	asm volatile ("wrpr %g0, %g0, %tl\n");
358	}	359	}
359		360
360	/** Read UPA_CONFIG register.	361	/** Read UPA_CONFIG register.
361	*	362	*
362	* @return Value of the UPA_CONFIG register.	363	* @return Value of the UPA_CONFIG register.
363	*/	364	*/
364	static inline uint64_t upa_config_read(void)	365	static inline uint64_t upa_config_read(void)
365	{	366	{
366	return asi_u64_read(ASI_UPA_CONFIG, 0);	367	return asi_u64_read(ASI_UPA_CONFIG, 0);
367	}	368	}
368		369
369	extern void cpu_halt(void);	370	extern void cpu_halt(void);
370	extern void cpu_sleep(void);	371	extern void cpu_sleep(void);
371	extern void asm_delay_loop(const uint32_t usec);	372	extern void asm_delay_loop(const uint32_t usec);
372		373
373	extern uint64_t read_from_ag_g7(void);	374	extern uint64_t read_from_ag_g7(void);
374	extern void write_to_ag_g6(uint64_t val);	375	extern void write_to_ag_g6(uint64_t val);
375	extern void write_to_ag_g7(uint64_t val);	376	extern void write_to_ag_g7(uint64_t val);
376	extern void write_to_ig_g6(uint64_t val);	377	extern void write_to_ig_g6(uint64_t val);
377		378
378	extern void switch_to_userspace(uint64_t pc, uint64_t sp, uint64_t uarg);	379	extern void switch_to_userspace(uint64_t pc, uint64_t sp, uint64_t uarg);
379		380
380	#endif	381	#endif
381		382
382	/** @}	383	/** @}
383	*/	384	*/
384		385