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1
/*
1
/*
2
 * Copyright (c) 2005 Martin Decky
2
 * Copyright (c) 2005 Martin Decky
3
 * All rights reserved.
3
 * All rights reserved.
4
 *
4
 *
5
 * Redistribution and use in source and binary forms, with or without
5
 * Redistribution and use in source and binary forms, with or without
6
 * modification, are permitted provided that the following conditions
6
 * modification, are permitted provided that the following conditions
7
 * are met:
7
 * are met:
8
 *
8
 *
9
 * - Redistributions of source code must retain the above copyright
9
 * - Redistributions of source code must retain the above copyright
10
 *   notice, this list of conditions and the following disclaimer.
10
 *   notice, this list of conditions and the following disclaimer.
11
 * - Redistributions in binary form must reproduce the above copyright
11
 * - Redistributions in binary form must reproduce the above copyright
12
 *   notice, this list of conditions and the following disclaimer in the
12
 *   notice, this list of conditions and the following disclaimer in the
13
 *   documentation and/or other materials provided with the distribution.
13
 *   documentation and/or other materials provided with the distribution.
14
 * - The name of the author may not be used to endorse or promote products
14
 * - The name of the author may not be used to endorse or promote products
15
 *   derived from this software without specific prior written permission.
15
 *   derived from this software without specific prior written permission.
16
 *
16
 *
17
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
21
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
25
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27
 */
27
 */
28
 
28
 
29
/** @addtogroup ppc64mm
29
/** @addtogroup ppc64mm
30
 * @{
30
 * @{
31
 */
31
 */
32
/** @file
32
/** @file
33
 */
33
 */
34
 
34
 
35
#include <arch/mm/page.h>
35
#include <arch/mm/page.h>
36
#include <genarch/mm/page_pt.h>
36
#include <genarch/mm/page_pt.h>
37
#include <arch/mm/frame.h>
37
#include <arch/mm/frame.h>
38
#include <arch/asm.h>
38
#include <arch/asm.h>
39
#include <mm/frame.h>
39
#include <mm/frame.h>
40
#include <mm/page.h>
40
#include <mm/page.h>
41
#include <mm/as.h>
41
#include <mm/as.h>
42
#include <arch.h>
42
#include <arch.h>
43
#include <arch/types.h>
43
#include <arch/types.h>
44
#include <arch/exception.h>
44
#include <arch/exception.h>
45
#include <align.h>
45
#include <align.h>
46
#include <config.h>
46
#include <config.h>
47
#include <print.h>
47
#include <print.h>
48
#include <symtab.h>
48
#include <symtab.h>
49
 
49
 
50
static phte_t *phte;
50
static phte_t *phte;
51
 
51
 
52
 
52
 
53
/** Try to find PTE for faulting address
53
/** Try to find PTE for faulting address
54
 *
54
 *
55
 * Try to find PTE for faulting address.
55
 * Try to find PTE for faulting address.
56
 * The as->lock must be held on entry to this function
56
 * The as->lock must be held on entry to this function
57
 * if lock is true.
57
 * if lock is true.
58
 *
58
 *
59
 * @param as       Address space.
59
 * @param as       Address space.
60
 * @param lock     Lock/unlock the address space.
60
 * @param lock     Lock/unlock the address space.
61
 * @param badvaddr Faulting virtual address.
61
 * @param badvaddr Faulting virtual address.
62
 * @param access   Access mode that caused the fault.
62
 * @param access   Access mode that caused the fault.
63
 * @param istate   Pointer to interrupted state.
63
 * @param istate   Pointer to interrupted state.
64
 * @param pfrc     Pointer to variable where as_page_fault() return code will be stored.
64
 * @param pfrc     Pointer to variable where as_page_fault() return code will be stored.
65
 * @return         PTE on success, NULL otherwise.
65
 * @return         PTE on success, NULL otherwise.
66
 *
66
 *
67
 */
67
 */
68
static pte_t *find_mapping_and_check(as_t *as, bool lock, uintptr_t badvaddr, int access,
68
static pte_t *find_mapping_and_check(as_t *as, bool lock, uintptr_t badvaddr, int access,
69
                     istate_t *istate, int *pfrc)
69
                     istate_t *istate, int *pfrc)
70
{
70
{
71
    /*
71
    /*
72
     * Check if the mapping exists in page tables.
72
     * Check if the mapping exists in page tables.
73
     */
73
     */
74
    pte_t *pte = page_mapping_find(as, badvaddr);
74
    pte_t *pte = page_mapping_find(as, badvaddr);
75
    if ((pte) && (pte->p)) {
75
    if ((pte) && (pte->p)) {
76
        /*
76
        /*
77
         * Mapping found in page tables.
77
         * Mapping found in page tables.
78
         * Immediately succeed.
78
         * Immediately succeed.
79
         */
79
         */
80
        return pte;
80
        return pte;
81
    } else {
81
    } else {
82
        int rc;
82
        int rc;
83
   
83
   
84
        /*
84
        /*
85
         * Mapping not found in page tables.
85
         * Mapping not found in page tables.
86
         * Resort to higher-level page fault handler.
86
         * Resort to higher-level page fault handler.
87
         */
87
         */
88
        page_table_unlock(as, lock);
88
        page_table_unlock(as, lock);
89
        switch (rc = as_page_fault(badvaddr, access, istate)) {
89
        switch (rc = as_page_fault(badvaddr, access, istate)) {
90
            case AS_PF_OK:
90
            case AS_PF_OK:
91
                /*
91
                /*
92
                 * The higher-level page fault handler succeeded,
92
                 * The higher-level page fault handler succeeded,
93
                 * The mapping ought to be in place.
93
                 * The mapping ought to be in place.
94
                 */
94
                 */
95
                page_table_lock(as, lock);
95
                page_table_lock(as, lock);
96
                pte = page_mapping_find(as, badvaddr);
96
                pte = page_mapping_find(as, badvaddr);
97
                ASSERT((pte) && (pte->p));
97
                ASSERT((pte) && (pte->p));
98
                *pfrc = 0;
98
                *pfrc = 0;
99
                return pte;
99
                return pte;
100
            case AS_PF_DEFER:
100
            case AS_PF_DEFER:
101
                page_table_lock(as, lock);
101
                page_table_lock(as, lock);
102
                *pfrc = rc;
102
                *pfrc = rc;
103
                return NULL;
103
                return NULL;
104
            case AS_PF_FAULT:
104
            case AS_PF_FAULT:
105
                page_table_lock(as, lock);
105
                page_table_lock(as, lock);
106
                *pfrc = rc;
106
                *pfrc = rc;
107
                return NULL;
107
                return NULL;
108
            default:
108
            default:
109
                panic("unexpected rc (%d)\n", rc);
109
                panic("Unexpected rc (%d).", rc);
110
        }  
110
        }  
111
    }
111
    }
112
}
112
}
113
 
113
 
114
 
114
 
115
static void pht_refill_fail(uintptr_t badvaddr, istate_t *istate)
115
static void pht_refill_fail(uintptr_t badvaddr, istate_t *istate)
116
{
116
{
117
    char *symbol = "";
117
    char *symbol = "";
118
    char *sym2 = "";
118
    char *sym2 = "";
119
 
119
 
120
    char *s = get_symtab_entry(istate->pc);
120
    char *s = get_symtab_entry(istate->pc);
121
    if (s)
121
    if (s)
122
        symbol = s;
122
        symbol = s;
123
    s = get_symtab_entry(istate->lr);
123
    s = get_symtab_entry(istate->lr);
124
    if (s)
124
    if (s)
125
        sym2 = s;
125
        sym2 = s;
126
    panic("%p: PHT Refill Exception at %p (%s<-%s)\n", badvaddr, istate->pc, symbol, sym2);
126
    panic("%p: PHT Refill Exception at %p (%s<-%s).", badvaddr, istate->pc, symbol, sym2);
127
}
127
}
128
 
128
 
129
 
129
 
130
static void pht_insert(const uintptr_t vaddr, const pfn_t pfn)
130
static void pht_insert(const uintptr_t vaddr, const pfn_t pfn)
131
{
131
{
132
    uint32_t page = (vaddr >> 12) & 0xffff;
132
    uint32_t page = (vaddr >> 12) & 0xffff;
133
    uint32_t api = (vaddr >> 22) & 0x3f;
133
    uint32_t api = (vaddr >> 22) & 0x3f;
134
    uint32_t vsid;
134
    uint32_t vsid;
135
   
135
   
136
    asm volatile (
136
    asm volatile (
137
        "mfsrin %0, %1\n"
137
        "mfsrin %0, %1\n"
138
        : "=r" (vsid)
138
        : "=r" (vsid)
139
        : "r" (vaddr)
139
        : "r" (vaddr)
140
    );
140
    );
141
   
141
   
142
    /* Primary hash (xor) */
142
    /* Primary hash (xor) */
143
    uint32_t h = 0;
143
    uint32_t h = 0;
144
    uint32_t hash = vsid ^ page;
144
    uint32_t hash = vsid ^ page;
145
    uint32_t base = (hash & 0x3ff) << 3;
145
    uint32_t base = (hash & 0x3ff) << 3;
146
    uint32_t i;
146
    uint32_t i;
147
    bool found = false;
147
    bool found = false;
148
   
148
   
149
    /* Find unused or colliding
149
    /* Find unused or colliding
150
       PTE in PTEG */
150
       PTE in PTEG */
151
    for (i = 0; i < 8; i++) {
151
    for (i = 0; i < 8; i++) {
152
        if ((!phte[base + i].v) || ((phte[base + i].vsid == vsid) && (phte[base + i].api == api))) {
152
        if ((!phte[base + i].v) || ((phte[base + i].vsid == vsid) && (phte[base + i].api == api))) {
153
            found = true;
153
            found = true;
154
            break;
154
            break;
155
        }
155
        }
156
    }
156
    }
157
   
157
   
158
    if (!found) {
158
    if (!found) {
159
        /* Secondary hash (not) */
159
        /* Secondary hash (not) */
160
        uint32_t base2 = (~hash & 0x3ff) << 3;
160
        uint32_t base2 = (~hash & 0x3ff) << 3;
161
       
161
       
162
        /* Find unused or colliding
162
        /* Find unused or colliding
163
           PTE in PTEG */
163
           PTE in PTEG */
164
        for (i = 0; i < 8; i++) {
164
        for (i = 0; i < 8; i++) {
165
            if ((!phte[base2 + i].v) || ((phte[base2 + i].vsid == vsid) && (phte[base2 + i].api == api))) {
165
            if ((!phte[base2 + i].v) || ((phte[base2 + i].vsid == vsid) && (phte[base2 + i].api == api))) {
166
                found = true;
166
                found = true;
167
                base = base2;
167
                base = base2;
168
                h = 1;
168
                h = 1;
169
                break;
169
                break;
170
            }
170
            }
171
        }
171
        }
172
       
172
       
173
        if (!found) {
173
        if (!found) {
174
            // TODO: A/C precedence groups
174
            // TODO: A/C precedence groups
175
            i = page % 8;
175
            i = page % 8;
176
        }
176
        }
177
    }
177
    }
178
   
178
   
179
    phte[base + i].v = 1;
179
    phte[base + i].v = 1;
180
    phte[base + i].vsid = vsid;
180
    phte[base + i].vsid = vsid;
181
    phte[base + i].h = h;
181
    phte[base + i].h = h;
182
    phte[base + i].api = api;
182
    phte[base + i].api = api;
183
    phte[base + i].rpn = pfn;
183
    phte[base + i].rpn = pfn;
184
    phte[base + i].r = 0;
184
    phte[base + i].r = 0;
185
    phte[base + i].c = 0;
185
    phte[base + i].c = 0;
186
    phte[base + i].pp = 2; // FIXME
186
    phte[base + i].pp = 2; // FIXME
187
}
187
}
188
 
188
 
189
 
189
 
190
/** Process Instruction/Data Storage Interrupt
190
/** Process Instruction/Data Storage Interrupt
191
 *
191
 *
192
 * @param data   True if Data Storage Interrupt.
192
 * @param data   True if Data Storage Interrupt.
193
 * @param istate Interrupted register context.
193
 * @param istate Interrupted register context.
194
 *
194
 *
195
 */
195
 */
196
void pht_refill(bool data, istate_t *istate)
196
void pht_refill(bool data, istate_t *istate)
197
{
197
{
198
    uintptr_t badvaddr;
198
    uintptr_t badvaddr;
199
    pte_t *pte;
199
    pte_t *pte;
200
    int pfrc;
200
    int pfrc;
201
    as_t *as;
201
    as_t *as;
202
    bool lock;
202
    bool lock;
203
   
203
   
204
    if (AS == NULL) {
204
    if (AS == NULL) {
205
        as = AS_KERNEL;
205
        as = AS_KERNEL;
206
        lock = false;
206
        lock = false;
207
    } else {
207
    } else {
208
        as = AS;
208
        as = AS;
209
        lock = true;
209
        lock = true;
210
    }
210
    }
211
   
211
   
212
    if (data) {
212
    if (data) {
213
        asm volatile (
213
        asm volatile (
214
            "mfdar %0\n"
214
            "mfdar %0\n"
215
            : "=r" (badvaddr)
215
            : "=r" (badvaddr)
216
        );
216
        );
217
    } else
217
    } else
218
        badvaddr = istate->pc;
218
        badvaddr = istate->pc;
219
       
219
       
220
    page_table_lock(as, lock);
220
    page_table_lock(as, lock);
221
   
221
   
222
    pte = find_mapping_and_check(as, lock, badvaddr, PF_ACCESS_READ /* FIXME */, istate, &pfrc);
222
    pte = find_mapping_and_check(as, lock, badvaddr, PF_ACCESS_READ /* FIXME */, istate, &pfrc);
223
    if (!pte) {
223
    if (!pte) {
224
        switch (pfrc) {
224
        switch (pfrc) {
225
            case AS_PF_FAULT:
225
            case AS_PF_FAULT:
226
                goto fail;
226
                goto fail;
227
                break;
227
                break;
228
            case AS_PF_DEFER:
228
            case AS_PF_DEFER:
229
                /*
229
                /*
230
                 * The page fault came during copy_from_uspace()
230
                 * The page fault came during copy_from_uspace()
231
                 * or copy_to_uspace().
231
                 * or copy_to_uspace().
232
                 */
232
                 */
233
                page_table_unlock(as, lock);
233
                page_table_unlock(as, lock);
234
                return;
234
                return;
235
            default:
235
            default:
236
                panic("Unexpected pfrc (%d)\n", pfrc);
236
                panic("Unexpected pfrc (%d).", pfrc);
237
        }
237
        }
238
    }
238
    }
239
   
239
   
240
    pte->a = 1; /* Record access to PTE */
240
    pte->a = 1; /* Record access to PTE */
241
    pht_insert(badvaddr, pte->pfn);
241
    pht_insert(badvaddr, pte->pfn);
242
   
242
   
243
    page_table_unlock(as, lock);
243
    page_table_unlock(as, lock);
244
    return;
244
    return;
245
   
245
   
246
fail:
246
fail:
247
    page_table_unlock(as, lock);
247
    page_table_unlock(as, lock);
248
    pht_refill_fail(badvaddr, istate);
248
    pht_refill_fail(badvaddr, istate);
249
}
249
}
250
 
250
 
251
 
251
 
252
void pht_init(void)
252
void pht_init(void)
253
{
253
{
254
    memsetb(phte, 1 << PHT_BITS, 0);
254
    memsetb(phte, 1 << PHT_BITS, 0);
255
}
255
}
256
 
256
 
257
 
257
 
258
void page_arch_init(void)
258
void page_arch_init(void)
259
{
259
{
260
    if (config.cpu_active == 1) {
260
    if (config.cpu_active == 1) {
261
        page_mapping_operations = &pt_mapping_operations;
261
        page_mapping_operations = &pt_mapping_operations;
262
       
262
       
263
        uintptr_t cur;
263
        uintptr_t cur;
264
        int flags;
264
        int flags;
265
       
265
       
266
        for (cur = 128 << 20; cur < last_frame; cur += FRAME_SIZE) {
266
        for (cur = 128 << 20; cur < last_frame; cur += FRAME_SIZE) {
267
            flags = PAGE_CACHEABLE | PAGE_WRITE;
267
            flags = PAGE_CACHEABLE | PAGE_WRITE;
268
            if ((PA2KA(cur) >= config.base) && (PA2KA(cur) < config.base + config.kernel_size))
268
            if ((PA2KA(cur) >= config.base) && (PA2KA(cur) < config.base + config.kernel_size))
269
                flags |= PAGE_GLOBAL;
269
                flags |= PAGE_GLOBAL;
270
            page_mapping_insert(AS_KERNEL, PA2KA(cur), cur, flags);
270
            page_mapping_insert(AS_KERNEL, PA2KA(cur), cur, flags);
271
        }
271
        }
272
       
272
       
273
        /* Allocate page hash table */
273
        /* Allocate page hash table */
274
        phte_t *physical_phte = (phte_t *) frame_alloc(PHT_ORDER, FRAME_KA | FRAME_ATOMIC);
274
        phte_t *physical_phte = (phte_t *) frame_alloc(PHT_ORDER, FRAME_KA | FRAME_ATOMIC);
275
       
275
       
276
        ASSERT((uintptr_t) physical_phte % (1 << PHT_BITS) == 0);
276
        ASSERT((uintptr_t) physical_phte % (1 << PHT_BITS) == 0);
277
        pht_init();
277
        pht_init();
278
       
278
       
279
        asm volatile (
279
        asm volatile (
280
            "mtsdr1 %0\n"
280
            "mtsdr1 %0\n"
281
            :
281
            :
282
            : "r" ((uintptr_t) physical_phte)
282
            : "r" ((uintptr_t) physical_phte)
283
        );
283
        );
284
    }
284
    }
285
}
285
}
286
 
286
 
287
 
287
 
288
uintptr_t hw_map(uintptr_t physaddr, size_t size)
288
uintptr_t hw_map(uintptr_t physaddr, size_t size)
289
{
289
{
290
    if (last_frame + ALIGN_UP(size, PAGE_SIZE) > KA2PA(KERNEL_ADDRESS_SPACE_END_ARCH))
290
    if (last_frame + ALIGN_UP(size, PAGE_SIZE) > KA2PA(KERNEL_ADDRESS_SPACE_END_ARCH))
291
        panic("Unable to map physical memory %p (%" PRIs " bytes)", physaddr, size)
291
        panic("Unable to map physical memory %p (%" PRIs " bytes).", physaddr, size)
292
   
292
   
293
    uintptr_t virtaddr = PA2KA(last_frame);
293
    uintptr_t virtaddr = PA2KA(last_frame);
294
    pfn_t i;
294
    pfn_t i;
295
    for (i = 0; i < ADDR2PFN(ALIGN_UP(size, PAGE_SIZE)); i++)
295
    for (i = 0; i < ADDR2PFN(ALIGN_UP(size, PAGE_SIZE)); i++)
296
        page_mapping_insert(AS_KERNEL, virtaddr + PFN2ADDR(i), physaddr + PFN2ADDR(i), PAGE_NOT_CACHEABLE | PAGE_WRITE);
296
        page_mapping_insert(AS_KERNEL, virtaddr + PFN2ADDR(i), physaddr + PFN2ADDR(i), PAGE_NOT_CACHEABLE | PAGE_WRITE);
297
   
297
   
298
    last_frame = ALIGN_UP(last_frame + size, FRAME_SIZE);
298
    last_frame = ALIGN_UP(last_frame + size, FRAME_SIZE);
299
   
299
   
300
    return virtaddr;
300
    return virtaddr;
301
}
301
}
302
 
302
 
303
/** @}
303
/** @}
304
 */
304
 */
305
 
305