WebSVN – HelenOS – Diff – /trunk/kernel/arch/mips32/src/asm.S


#
# Copyright (c) 2003-2004 Jakub Jermar
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions
# are met:
#
# - Redistributions of source code must retain the above copyright
#   notice, this list of conditions and the following disclaimer.
# - Redistributions in binary form must reproduce the above copyright
#   notice, this list of conditions and the following disclaimer in the
#   documentation and/or other materials provided with the distribution.
# - The name of the author may not be used to endorse or promote products
#   derived from this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
 
#include <arch/asm/regname.h>
	
.text
 
.macro cp0_read reg
	mfc0 $2,\reg
	j $31
	nop
.endm
 
.macro cp0_write reg
	mtc0 $4,\reg
	j $31
	nop
.endm
 
.set noat
.set noreorder
.set nomacro
 
.global cpu_halt
cpu_halt:
	j cpu_halt
	nop
 
 
.global memsetb
memsetb:
	j _memsetb
	nop
 
 
.global memcpy
.global memcpy_from_uspace
.global memcpy_to_uspace
.global memcpy_from_uspace_failover_address
.global memcpy_to_uspace_failover_address
memcpy:
memcpy_from_uspace:
memcpy_to_uspace:
	addiu	$v0,$a1,3
	li	$v1,-4			# 0xfffffffffffffffc
	and	$v0,$v0,$v1
	beq	$a1,$v0,3f
	move	$t0,$a0
 
0:
	beq	$a2,$zero,2f
	move	$a3,$zero
 
1:
	addu	$v0,$a1,$a3
	lbu	$a0,0($v0)
	addu	$v1,$t0,$a3
	addiu	$a3,$a3,1
	bne	$a3,$a2,1b
	sb	$a0,0($v1)
 
2:
	jr	$ra
	move	$v0,$a1
 
3:
	addiu	$v0,$a0,3
	and	$v0,$v0,$v1
	bne	$a0,$v0,0b
	srl	$t1,$a2,2
 
	beq	$t1,$zero,5f
	move	$a3,$zero
 
	move	$a3,$zero
	move	$a0,$zero
4:
	addu	$v0,$a1,$a0
	lw	$v1,0($v0)
	addiu	$a3,$a3,1
	addu	$v0,$t0,$a0
	sw	$v1,0($v0)
	bne	$a3,$t1,4b
	addiu	$a0,$a0,4
 
5:
	andi	$a2,$a2,0x3
	beq	$a2,$zero,2b
	nop
 
	sll	$v0,$a3,2
	addu	$t1,$v0,$t0
	move	$a3,$zero
	addu	$t0,$v0,$a1
6:
	addu	$v0,$t0,$a3
	lbu	$a0,0($v0)
	addu	$v1,$t1,$a3
	addiu	$a3,$a3,1
	bne	$a3,$a2,6b
	sb	$a0,0($v1)
 
	jr	$ra
	move	$v0,$a1
 
memcpy_from_uspace_failover_address:
memcpy_to_uspace_failover_address:
	jr	$ra
	move	$v0, $zero
 
 
 
.macro fpu_gp_save reg ctx
	mfc1 $t0,$\reg
	sw $t0, \reg*4(\ctx)
.endm
 
.macro fpu_gp_restore reg ctx
	lw $t0, \reg*4(\ctx)
	mtc1 $t0,$\reg
.endm
 
.macro fpu_ct_save reg ctx
	cfc1 $t0,$1
	sw $t0, (\reg+32)*4(\ctx)
.endm	
 
.macro fpu_ct_restore reg ctx
	lw $t0, (\reg+32)*4(\ctx)
	ctc1 $t0,$\reg
.endm
 
 
.global fpu_context_save
fpu_context_save:
#ifdef ARCH_HAS_FPU
	fpu_gp_save 0,$a0
	fpu_gp_save 1,$a0
	fpu_gp_save 2,$a0
	fpu_gp_save 3,$a0
	fpu_gp_save 4,$a0
	fpu_gp_save 5,$a0
	fpu_gp_save 6,$a0
	fpu_gp_save 7,$a0
	fpu_gp_save 8,$a0
	fpu_gp_save 9,$a0
	fpu_gp_save 10,$a0
	fpu_gp_save 11,$a0
	fpu_gp_save 12,$a0
	fpu_gp_save 13,$a0
	fpu_gp_save 14,$a0
	fpu_gp_save 15,$a0
	fpu_gp_save 16,$a0
	fpu_gp_save 17,$a0
	fpu_gp_save 18,$a0
	fpu_gp_save 19,$a0
	fpu_gp_save 20,$a0
	fpu_gp_save 21,$a0
	fpu_gp_save 22,$a0
	fpu_gp_save 23,$a0
	fpu_gp_save 24,$a0
	fpu_gp_save 25,$a0
	fpu_gp_save 26,$a0
	fpu_gp_save 27,$a0
	fpu_gp_save 28,$a0
	fpu_gp_save 29,$a0
	fpu_gp_save 30,$a0
	fpu_gp_save 31,$a0
 
	fpu_ct_save 1,$a0
	fpu_ct_save 2,$a0
	fpu_ct_save 3,$a0
	fpu_ct_save 4,$a0
	fpu_ct_save 5,$a0
	fpu_ct_save 6,$a0
	fpu_ct_save 7,$a0
	fpu_ct_save 8,$a0
	fpu_ct_save 9,$a0
	fpu_ct_save 10,$a0
	fpu_ct_save 11,$a0
	fpu_ct_save 12,$a0
	fpu_ct_save 13,$a0
	fpu_ct_save 14,$a0
	fpu_ct_save 15,$a0
	fpu_ct_save 16,$a0
	fpu_ct_save 17,$a0
	fpu_ct_save 18,$a0
	fpu_ct_save 19,$a0
	fpu_ct_save 20,$a0
	fpu_ct_save 21,$a0
	fpu_ct_save 22,$a0
	fpu_ct_save 23,$a0
	fpu_ct_save 24,$a0
	fpu_ct_save 25,$a0
	fpu_ct_save 26,$a0
	fpu_ct_save 27,$a0
	fpu_ct_save 28,$a0
	fpu_ct_save 29,$a0
	fpu_ct_save 30,$a0
	fpu_ct_save 31,$a0
#endif		
	j $ra
	nop
 
.global fpu_context_restore
fpu_context_restore:
#ifdef ARCH_HAS_FPU
	fpu_gp_restore 0,$a0
	fpu_gp_restore 1,$a0
	fpu_gp_restore 2,$a0
	fpu_gp_restore 3,$a0
	fpu_gp_restore 4,$a0
	fpu_gp_restore 5,$a0
	fpu_gp_restore 6,$a0
	fpu_gp_restore 7,$a0
	fpu_gp_restore 8,$a0
	fpu_gp_restore 9,$a0
	fpu_gp_restore 10,$a0
	fpu_gp_restore 11,$a0
	fpu_gp_restore 12,$a0
	fpu_gp_restore 13,$a0
	fpu_gp_restore 14,$a0
	fpu_gp_restore 15,$a0
	fpu_gp_restore 16,$a0
	fpu_gp_restore 17,$a0
	fpu_gp_restore 18,$a0
	fpu_gp_restore 19,$a0
	fpu_gp_restore 20,$a0
	fpu_gp_restore 21,$a0
	fpu_gp_restore 22,$a0
	fpu_gp_restore 23,$a0
	fpu_gp_restore 24,$a0
	fpu_gp_restore 25,$a0
	fpu_gp_restore 26,$a0
	fpu_gp_restore 27,$a0
	fpu_gp_restore 28,$a0
	fpu_gp_restore 29,$a0
	fpu_gp_restore 30,$a0
	fpu_gp_restore 31,$a0
 
	fpu_ct_restore 1,$a0
	fpu_ct_restore 2,$a0
	fpu_ct_restore 3,$a0
	fpu_ct_restore 4,$a0
	fpu_ct_restore 5,$a0
	fpu_ct_restore 6,$a0
	fpu_ct_restore 7,$a0
	fpu_ct_restore 8,$a0
	fpu_ct_restore 9,$a0
	fpu_ct_restore 10,$a0
	fpu_ct_restore 11,$a0
	fpu_ct_restore 12,$a0
	fpu_ct_restore 13,$a0
	fpu_ct_restore 14,$a0
	fpu_ct_restore 15,$a0
	fpu_ct_restore 16,$a0
	fpu_ct_restore 17,$a0
	fpu_ct_restore 18,$a0
	fpu_ct_restore 19,$a0
	fpu_ct_restore 20,$a0
	fpu_ct_restore 21,$a0
	fpu_ct_restore 22,$a0
	fpu_ct_restore 23,$a0
	fpu_ct_restore 24,$a0
	fpu_ct_restore 25,$a0
	fpu_ct_restore 26,$a0
	fpu_ct_restore 27,$a0
	fpu_ct_restore 28,$a0
	fpu_ct_restore 29,$a0
	fpu_ct_restore 30,$a0
	fpu_ct_restore 31,$a0
#endif	
	j $ra
	nop
 

Rev 1787	Rev 2071
1	#	1	#
2	# Copyright (C) 2003-2004 Jakub Jermar	2	# Copyright (c) 2003-2004 Jakub Jermar
3	# All rights reserved.	3	# All rights reserved.
4	#	4	#
5	# Redistribution and use in source and binary forms, with or without	5	# Redistribution and use in source and binary forms, with or without
6	# modification, are permitted provided that the following conditions	6	# modification, are permitted provided that the following conditions
7	# are met:	7	# are met:
8	#	8	#
9	# - Redistributions of source code must retain the above copyright	9	# - Redistributions of source code must retain the above copyright
10	# notice, this list of conditions and the following disclaimer.	10	# notice, this list of conditions and the following disclaimer.
11	# - Redistributions in binary form must reproduce the above copyright	11	# - Redistributions in binary form must reproduce the above copyright
12	# notice, this list of conditions and the following disclaimer in the	12	# notice, this list of conditions and the following disclaimer in the
13	# documentation and/or other materials provided with the distribution.	13	# documentation and/or other materials provided with the distribution.
14	# - The name of the author may not be used to endorse or promote products	14	# - The name of the author may not be used to endorse or promote products
15	# derived from this software without specific prior written permission.	15	# derived from this software without specific prior written permission.
16	#	16	#
17	# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	17	# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18	# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	18	# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19	# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	19	# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20	# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	20	# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21	# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	21	# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22	# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	22	# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23	# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	23	# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24	# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	24	# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25	# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	25	# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26	# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	26	# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27	#	27	#
28		28
29	#include <arch/asm/regname.h>	29	#include <arch/asm/regname.h>
30		30
31	.text	31	.text
32		32
33	.macro cp0_read reg	33	.macro cp0_read reg
34	mfc0 $2,\reg	34	mfc0 $2,\reg
35	j $31	35	j $31
36	nop	36	nop
37	.endm	37	.endm
38		38
39	.macro cp0_write reg	39	.macro cp0_write reg
40	mtc0 $4,\reg	40	mtc0 $4,\reg
41	j $31	41	j $31
42	nop	42	nop
43	.endm	43	.endm
44		44
45	.set noat	45	.set noat
46	.set noreorder	46	.set noreorder
47	.set nomacro	47	.set nomacro
48		48
49	.global cpu_halt	49	.global cpu_halt
50	cpu_halt:	50	cpu_halt:
51	j cpu_halt	51	j cpu_halt
52	nop	52	nop
53		53
54		54
55	.global memsetb	55	.global memsetb
56	memsetb:	56	memsetb:
57	j _memsetb	57	j _memsetb
58	nop	58	nop
59		59
60		60
61	.global memcpy	61	.global memcpy
62	.global memcpy_from_uspace	62	.global memcpy_from_uspace
63	.global memcpy_to_uspace	63	.global memcpy_to_uspace
64	.global memcpy_from_uspace_failover_address	64	.global memcpy_from_uspace_failover_address
65	.global memcpy_to_uspace_failover_address	65	.global memcpy_to_uspace_failover_address
66	memcpy:	66	memcpy:
67	memcpy_from_uspace:	67	memcpy_from_uspace:
68	memcpy_to_uspace:	68	memcpy_to_uspace:
69	addiu $v0,$a1,3	69	addiu $v0,$a1,3
70	li $v1,-4 # 0xfffffffffffffffc	70	li $v1,-4 # 0xfffffffffffffffc
71	and $v0,$v0,$v1	71	and $v0,$v0,$v1
72	beq $a1,$v0,3f	72	beq $a1,$v0,3f
73	move $t0,$a0	73	move $t0,$a0
74		74
75	0:	75	0:
76	beq $a2,$zero,2f	76	beq $a2,$zero,2f
77	move $a3,$zero	77	move $a3,$zero
78		78
79	1:	79	1:
80	addu $v0,$a1,$a3	80	addu $v0,$a1,$a3
81	lbu $a0,0($v0)	81	lbu $a0,0($v0)
82	addu $v1,$t0,$a3	82	addu $v1,$t0,$a3
83	addiu $a3,$a3,1	83	addiu $a3,$a3,1
84	bne $a3,$a2,1b	84	bne $a3,$a2,1b
85	sb $a0,0($v1)	85	sb $a0,0($v1)
86		86
87	2:	87	2:
88	jr $ra	88	jr $ra
89	move $v0,$a1	89	move $v0,$a1
90		90
91	3:	91	3:
92	addiu $v0,$a0,3	92	addiu $v0,$a0,3
93	and $v0,$v0,$v1	93	and $v0,$v0,$v1
94	bne $a0,$v0,0b	94	bne $a0,$v0,0b
95	srl $t1,$a2,2	95	srl $t1,$a2,2
96		96
97	beq $t1,$zero,5f	97	beq $t1,$zero,5f
98	move $a3,$zero	98	move $a3,$zero
99		99
100	move $a3,$zero	100	move $a3,$zero
101	move $a0,$zero	101	move $a0,$zero
102	4:	102	4:
103	addu $v0,$a1,$a0	103	addu $v0,$a1,$a0
104	lw $v1,0($v0)	104	lw $v1,0($v0)
105	addiu $a3,$a3,1	105	addiu $a3,$a3,1
106	addu $v0,$t0,$a0	106	addu $v0,$t0,$a0
107	sw $v1,0($v0)	107	sw $v1,0($v0)
108	bne $a3,$t1,4b	108	bne $a3,$t1,4b
109	addiu $a0,$a0,4	109	addiu $a0,$a0,4
110		110
111	5:	111	5:
112	andi $a2,$a2,0x3	112	andi $a2,$a2,0x3
113	beq $a2,$zero,2b	113	beq $a2,$zero,2b
114	nop	114	nop
115		115
116	sll $v0,$a3,2	116	sll $v0,$a3,2
117	addu $t1,$v0,$t0	117	addu $t1,$v0,$t0
118	move $a3,$zero	118	move $a3,$zero
119	addu $t0,$v0,$a1	119	addu $t0,$v0,$a1
120	6:	120	6:
121	addu $v0,$t0,$a3	121	addu $v0,$t0,$a3
122	lbu $a0,0($v0)	122	lbu $a0,0($v0)
123	addu $v1,$t1,$a3	123	addu $v1,$t1,$a3
124	addiu $a3,$a3,1	124	addiu $a3,$a3,1
125	bne $a3,$a2,6b	125	bne $a3,$a2,6b
126	sb $a0,0($v1)	126	sb $a0,0($v1)
127		127
128	jr $ra	128	jr $ra
129	move $v0,$a1	129	move $v0,$a1
130		130
131	memcpy_from_uspace_failover_address:	131	memcpy_from_uspace_failover_address:
132	memcpy_to_uspace_failover_address:	132	memcpy_to_uspace_failover_address:
133	jr $ra	133	jr $ra
134	move $v0, $zero	134	move $v0, $zero
135		135
136		136
137		137
138	.macro fpu_gp_save reg ctx	138	.macro fpu_gp_save reg ctx
139	mfc1 $t0,$\reg	139	mfc1 $t0,$\reg
140	sw $t0, \reg*4(\ctx)	140	sw $t0, \reg*4(\ctx)
141	.endm	141	.endm
142		142
143	.macro fpu_gp_restore reg ctx	143	.macro fpu_gp_restore reg ctx
144	lw $t0, \reg*4(\ctx)	144	lw $t0, \reg*4(\ctx)
145	mtc1 $t0,$\reg	145	mtc1 $t0,$\reg
146	.endm	146	.endm
147		147
148	.macro fpu_ct_save reg ctx	148	.macro fpu_ct_save reg ctx
149	cfc1 $t0,$1	149	cfc1 $t0,$1
150	sw $t0, (\reg+32)*4(\ctx)	150	sw $t0, (\reg+32)*4(\ctx)
151	.endm	151	.endm
152		152
153	.macro fpu_ct_restore reg ctx	153	.macro fpu_ct_restore reg ctx
154	lw $t0, (\reg+32)*4(\ctx)	154	lw $t0, (\reg+32)*4(\ctx)
155	ctc1 $t0,$\reg	155	ctc1 $t0,$\reg
156	.endm	156	.endm
157		157
158		158
159	.global fpu_context_save	159	.global fpu_context_save
160	fpu_context_save:	160	fpu_context_save:
161	#ifdef ARCH_HAS_FPU	161	#ifdef ARCH_HAS_FPU
162	fpu_gp_save 0,$a0	162	fpu_gp_save 0,$a0
163	fpu_gp_save 1,$a0	163	fpu_gp_save 1,$a0
164	fpu_gp_save 2,$a0	164	fpu_gp_save 2,$a0
165	fpu_gp_save 3,$a0	165	fpu_gp_save 3,$a0
166	fpu_gp_save 4,$a0	166	fpu_gp_save 4,$a0
167	fpu_gp_save 5,$a0	167	fpu_gp_save 5,$a0
168	fpu_gp_save 6,$a0	168	fpu_gp_save 6,$a0
169	fpu_gp_save 7,$a0	169	fpu_gp_save 7,$a0
170	fpu_gp_save 8,$a0	170	fpu_gp_save 8,$a0
171	fpu_gp_save 9,$a0	171	fpu_gp_save 9,$a0
172	fpu_gp_save 10,$a0	172	fpu_gp_save 10,$a0
173	fpu_gp_save 11,$a0	173	fpu_gp_save 11,$a0
174	fpu_gp_save 12,$a0	174	fpu_gp_save 12,$a0
175	fpu_gp_save 13,$a0	175	fpu_gp_save 13,$a0
176	fpu_gp_save 14,$a0	176	fpu_gp_save 14,$a0
177	fpu_gp_save 15,$a0	177	fpu_gp_save 15,$a0
178	fpu_gp_save 16,$a0	178	fpu_gp_save 16,$a0
179	fpu_gp_save 17,$a0	179	fpu_gp_save 17,$a0
180	fpu_gp_save 18,$a0	180	fpu_gp_save 18,$a0
181	fpu_gp_save 19,$a0	181	fpu_gp_save 19,$a0
182	fpu_gp_save 20,$a0	182	fpu_gp_save 20,$a0
183	fpu_gp_save 21,$a0	183	fpu_gp_save 21,$a0
184	fpu_gp_save 22,$a0	184	fpu_gp_save 22,$a0
185	fpu_gp_save 23,$a0	185	fpu_gp_save 23,$a0
186	fpu_gp_save 24,$a0	186	fpu_gp_save 24,$a0
187	fpu_gp_save 25,$a0	187	fpu_gp_save 25,$a0
188	fpu_gp_save 26,$a0	188	fpu_gp_save 26,$a0
189	fpu_gp_save 27,$a0	189	fpu_gp_save 27,$a0
190	fpu_gp_save 28,$a0	190	fpu_gp_save 28,$a0
191	fpu_gp_save 29,$a0	191	fpu_gp_save 29,$a0
192	fpu_gp_save 30,$a0	192	fpu_gp_save 30,$a0
193	fpu_gp_save 31,$a0	193	fpu_gp_save 31,$a0
194		194
195	fpu_ct_save 1,$a0	195	fpu_ct_save 1,$a0
196	fpu_ct_save 2,$a0	196	fpu_ct_save 2,$a0
197	fpu_ct_save 3,$a0	197	fpu_ct_save 3,$a0
198	fpu_ct_save 4,$a0	198	fpu_ct_save 4,$a0
199	fpu_ct_save 5,$a0	199	fpu_ct_save 5,$a0
200	fpu_ct_save 6,$a0	200	fpu_ct_save 6,$a0
201	fpu_ct_save 7,$a0	201	fpu_ct_save 7,$a0
202	fpu_ct_save 8,$a0	202	fpu_ct_save 8,$a0
203	fpu_ct_save 9,$a0	203	fpu_ct_save 9,$a0
204	fpu_ct_save 10,$a0	204	fpu_ct_save 10,$a0
205	fpu_ct_save 11,$a0	205	fpu_ct_save 11,$a0
206	fpu_ct_save 12,$a0	206	fpu_ct_save 12,$a0
207	fpu_ct_save 13,$a0	207	fpu_ct_save 13,$a0
208	fpu_ct_save 14,$a0	208	fpu_ct_save 14,$a0
209	fpu_ct_save 15,$a0	209	fpu_ct_save 15,$a0
210	fpu_ct_save 16,$a0	210	fpu_ct_save 16,$a0
211	fpu_ct_save 17,$a0	211	fpu_ct_save 17,$a0
212	fpu_ct_save 18,$a0	212	fpu_ct_save 18,$a0
213	fpu_ct_save 19,$a0	213	fpu_ct_save 19,$a0
214	fpu_ct_save 20,$a0	214	fpu_ct_save 20,$a0
215	fpu_ct_save 21,$a0	215	fpu_ct_save 21,$a0
216	fpu_ct_save 22,$a0	216	fpu_ct_save 22,$a0
217	fpu_ct_save 23,$a0	217	fpu_ct_save 23,$a0
218	fpu_ct_save 24,$a0	218	fpu_ct_save 24,$a0
219	fpu_ct_save 25,$a0	219	fpu_ct_save 25,$a0
220	fpu_ct_save 26,$a0	220	fpu_ct_save 26,$a0
221	fpu_ct_save 27,$a0	221	fpu_ct_save 27,$a0
222	fpu_ct_save 28,$a0	222	fpu_ct_save 28,$a0
223	fpu_ct_save 29,$a0	223	fpu_ct_save 29,$a0
224	fpu_ct_save 30,$a0	224	fpu_ct_save 30,$a0
225	fpu_ct_save 31,$a0	225	fpu_ct_save 31,$a0
226	#endif	226	#endif
227	j $ra	227	j $ra
228	nop	228	nop
229		229
230	.global fpu_context_restore	230	.global fpu_context_restore
231	fpu_context_restore:	231	fpu_context_restore:
232	#ifdef ARCH_HAS_FPU	232	#ifdef ARCH_HAS_FPU
233	fpu_gp_restore 0,$a0	233	fpu_gp_restore 0,$a0
234	fpu_gp_restore 1,$a0	234	fpu_gp_restore 1,$a0
235	fpu_gp_restore 2,$a0	235	fpu_gp_restore 2,$a0
236	fpu_gp_restore 3,$a0	236	fpu_gp_restore 3,$a0
237	fpu_gp_restore 4,$a0	237	fpu_gp_restore 4,$a0
238	fpu_gp_restore 5,$a0	238	fpu_gp_restore 5,$a0
239	fpu_gp_restore 6,$a0	239	fpu_gp_restore 6,$a0
240	fpu_gp_restore 7,$a0	240	fpu_gp_restore 7,$a0
241	fpu_gp_restore 8,$a0	241	fpu_gp_restore 8,$a0
242	fpu_gp_restore 9,$a0	242	fpu_gp_restore 9,$a0
243	fpu_gp_restore 10,$a0	243	fpu_gp_restore 10,$a0
244	fpu_gp_restore 11,$a0	244	fpu_gp_restore 11,$a0
245	fpu_gp_restore 12,$a0	245	fpu_gp_restore 12,$a0
246	fpu_gp_restore 13,$a0	246	fpu_gp_restore 13,$a0
247	fpu_gp_restore 14,$a0	247	fpu_gp_restore 14,$a0
248	fpu_gp_restore 15,$a0	248	fpu_gp_restore 15,$a0
249	fpu_gp_restore 16,$a0	249	fpu_gp_restore 16,$a0
250	fpu_gp_restore 17,$a0	250	fpu_gp_restore 17,$a0
251	fpu_gp_restore 18,$a0	251	fpu_gp_restore 18,$a0
252	fpu_gp_restore 19,$a0	252	fpu_gp_restore 19,$a0
253	fpu_gp_restore 20,$a0	253	fpu_gp_restore 20,$a0
254	fpu_gp_restore 21,$a0	254	fpu_gp_restore 21,$a0
255	fpu_gp_restore 22,$a0	255	fpu_gp_restore 22,$a0
256	fpu_gp_restore 23,$a0	256	fpu_gp_restore 23,$a0
257	fpu_gp_restore 24,$a0	257	fpu_gp_restore 24,$a0
258	fpu_gp_restore 25,$a0	258	fpu_gp_restore 25,$a0
259	fpu_gp_restore 26,$a0	259	fpu_gp_restore 26,$a0
260	fpu_gp_restore 27,$a0	260	fpu_gp_restore 27,$a0
261	fpu_gp_restore 28,$a0	261	fpu_gp_restore 28,$a0
262	fpu_gp_restore 29,$a0	262	fpu_gp_restore 29,$a0
263	fpu_gp_restore 30,$a0	263	fpu_gp_restore 30,$a0
264	fpu_gp_restore 31,$a0	264	fpu_gp_restore 31,$a0
265		265
266	fpu_ct_restore 1,$a0	266	fpu_ct_restore 1,$a0
267	fpu_ct_restore 2,$a0	267	fpu_ct_restore 2,$a0
268	fpu_ct_restore 3,$a0	268	fpu_ct_restore 3,$a0
269	fpu_ct_restore 4,$a0	269	fpu_ct_restore 4,$a0
270	fpu_ct_restore 5,$a0	270	fpu_ct_restore 5,$a0
271	fpu_ct_restore 6,$a0	271	fpu_ct_restore 6,$a0
272	fpu_ct_restore 7,$a0	272	fpu_ct_restore 7,$a0
273	fpu_ct_restore 8,$a0	273	fpu_ct_restore 8,$a0
274	fpu_ct_restore 9,$a0	274	fpu_ct_restore 9,$a0
275	fpu_ct_restore 10,$a0	275	fpu_ct_restore 10,$a0
276	fpu_ct_restore 11,$a0	276	fpu_ct_restore 11,$a0
277	fpu_ct_restore 12,$a0	277	fpu_ct_restore 12,$a0
278	fpu_ct_restore 13,$a0	278	fpu_ct_restore 13,$a0
279	fpu_ct_restore 14,$a0	279	fpu_ct_restore 14,$a0
280	fpu_ct_restore 15,$a0	280	fpu_ct_restore 15,$a0
281	fpu_ct_restore 16,$a0	281	fpu_ct_restore 16,$a0
282	fpu_ct_restore 17,$a0	282	fpu_ct_restore 17,$a0
283	fpu_ct_restore 18,$a0	283	fpu_ct_restore 18,$a0
284	fpu_ct_restore 19,$a0	284	fpu_ct_restore 19,$a0
285	fpu_ct_restore 20,$a0	285	fpu_ct_restore 20,$a0
286	fpu_ct_restore 21,$a0	286	fpu_ct_restore 21,$a0
287	fpu_ct_restore 22,$a0	287	fpu_ct_restore 22,$a0
288	fpu_ct_restore 23,$a0	288	fpu_ct_restore 23,$a0
289	fpu_ct_restore 24,$a0	289	fpu_ct_restore 24,$a0
290	fpu_ct_restore 25,$a0	290	fpu_ct_restore 25,$a0
291	fpu_ct_restore 26,$a0	291	fpu_ct_restore 26,$a0
292	fpu_ct_restore 27,$a0	292	fpu_ct_restore 27,$a0
293	fpu_ct_restore 28,$a0	293	fpu_ct_restore 28,$a0
294	fpu_ct_restore 29,$a0	294	fpu_ct_restore 29,$a0
295	fpu_ct_restore 30,$a0	295	fpu_ct_restore 30,$a0
296	fpu_ct_restore 31,$a0	296	fpu_ct_restore 31,$a0
297	#endif	297	#endif
298	j $ra	298	j $ra
299	nop	299	nop
300		300

Subversion Repositories HelenOS

(root)/trunk/kernel/arch/mips32/src/asm.S – Rev 1787 → 2071