WebSVN – HelenOS – Diff – /trunk/kernel/arch/mips32/include/mm/tlb.h


/*
 * Copyright (c) 2003-2004 Jakub Jermar
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * - Redistributions of source code must retain the above copyright
 *   notice, this list of conditions and the following disclaimer.
 * - Redistributions in binary form must reproduce the above copyright
 *   notice, this list of conditions and the following disclaimer in the
 *   documentation and/or other materials provided with the distribution.
 * - The name of the author may not be used to endorse or promote products
 *   derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
/** @addtogroup mips32mm   
 * @{
 */
/** @file
 */
 
#ifndef KERN_mips32_TLB_H_
#define KERN_mips32_TLB_H_
 
#include <arch/exception.h>
 
 
#ifdef TLBCNT
#   define TLB_ENTRY_COUNT      TLBCNT
#else
#   define TLB_ENTRY_COUNT      48
#endif
 
#define TLB_WIRED       1
#define TLB_KSTACK_WIRED_INDEX  0
 
#define TLB_PAGE_MASK_16K   (0x3<<13)
 
#define PAGE_UNCACHED           2
#define PAGE_CACHEABLE_EXC_WRITE    5
 
 
 
 
typedef union {
 
 
    struct {
#ifdef BIG_ENDIAN
        unsigned : 2;       /* zero */
        unsigned pfn : 24;  /* frame number */
        unsigned c : 3;     /* cache coherency attribute */
        unsigned d : 1;     /* dirty/write-protect bit */
        unsigned v : 1;     /* valid bit */
        unsigned g : 1;     /* global bit */
#else
        unsigned g : 1;     /* global bit */
        unsigned v : 1;     /* valid bit */
        unsigned d : 1;     /* dirty/write-protect bit */
        unsigned c : 3;     /* cache coherency attribute */
        unsigned pfn : 24;  /* frame number */
        unsigned : 2;       /* zero */
#endif
    } __attribute__ ((packed));
    uint32_t value;
 
 
 
} entry_lo_t;
 
 
 
 
 
 
 
 
 
 
 
typedef union {
    struct {
#ifdef BIG_ENDIAN
        unsigned vpn2 : 19;
        unsigned : 5;
        unsigned asid : 8;
#else
        unsigned asid : 8;
        unsigned : 5;
        unsigned vpn2 : 19;
#endif
    } __attribute__ ((packed));
    uint32_t value;
} entry_hi_t;
 
typedef union {
    struct {
#ifdef BIG_ENDIAN
        unsigned : 7;
        unsigned mask : 12;
        unsigned : 13;
#else
        unsigned : 13;
        unsigned mask : 12;
        unsigned : 7;
#endif
    } __attribute__ ((packed));
    uint32_t value;
} page_mask_t;
 
typedef union {
    struct {
#ifdef BIG_ENDIAN
        unsigned p : 1;
        unsigned : 27;
        unsigned index : 4;
#else
        unsigned index : 4;
        unsigned : 27;
        unsigned p : 1;
#endif
    } __attribute__ ((packed));
    uint32_t value;
} tlb_index_t;
 
/** Probe TLB for Matching Entry
 *
 * Probe TLB for Matching Entry.
 */
static inline void tlbp(void)
{
    asm volatile ("tlbp\n\t");
}
 
 
/** Read Indexed TLB Entry
 *
 * Read Indexed TLB Entry.
 */
static inline void tlbr(void)
{
    asm volatile ("tlbr\n\t");
}
 
/** Write Indexed TLB Entry
 *
 * Write Indexed TLB Entry.
 */
static inline void tlbwi(void)
{
    asm volatile ("tlbwi\n\t");
}
 
/** Write Random TLB Entry
 *
 * Write Random TLB Entry.
 */
static inline void tlbwr(void)
{
    asm volatile ("tlbwr\n\t");
}
 
#define tlb_invalidate(asid)    tlb_invalidate_asid(asid)
 
extern void tlb_invalid(istate_t *istate);
extern void tlb_refill(istate_t *istate);
extern void tlb_modified(istate_t *istate);
 
#endif
 
/** @}
 */
 

Rev 2082	Rev 2089
1	/*	1	/*
2	* Copyright (c) 2003-2004 Jakub Jermar	2	* Copyright (c) 2003-2004 Jakub Jermar
3	* All rights reserved.	3	* All rights reserved.
4	*	4	*
5	* Redistribution and use in source and binary forms, with or without	5	* Redistribution and use in source and binary forms, with or without
6	* modification, are permitted provided that the following conditions	6	* modification, are permitted provided that the following conditions
7	* are met:	7	* are met:
8	*	8	*
9	* - Redistributions of source code must retain the above copyright	9	* - Redistributions of source code must retain the above copyright
10	* notice, this list of conditions and the following disclaimer.	10	* notice, this list of conditions and the following disclaimer.
11	* - Redistributions in binary form must reproduce the above copyright	11	* - Redistributions in binary form must reproduce the above copyright
12	* notice, this list of conditions and the following disclaimer in the	12	* notice, this list of conditions and the following disclaimer in the
13	* documentation and/or other materials provided with the distribution.	13	* documentation and/or other materials provided with the distribution.
14	* - The name of the author may not be used to endorse or promote products	14	* - The name of the author may not be used to endorse or promote products
15	* derived from this software without specific prior written permission.	15	* derived from this software without specific prior written permission.
16	*	16	*
17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27	*/	27	*/
28		28
29	/** @addtogroup mips32mm	29	/** @addtogroup mips32mm
30	* @{	30	* @{
31	*/	31	*/
32	/** @file	32	/** @file
33	*/	33	*/
34		34
35	#ifndef KERN_mips32_TLB_H_	35	#ifndef KERN_mips32_TLB_H_
36	#define KERN_mips32_TLB_H_	36	#define KERN_mips32_TLB_H_
37		37
38	#include <arch/exception.h>	38	#include <arch/exception.h>
39	#include <typedefs.h>	-
40		39
41	#ifdef TLBCNT	40	#ifdef TLBCNT
42	# define TLB_ENTRY_COUNT TLBCNT	41	# define TLB_ENTRY_COUNT TLBCNT
43	#else	42	#else
44	# define TLB_ENTRY_COUNT 48	43	# define TLB_ENTRY_COUNT 48
45	#endif	44	#endif
46		45
47	#define TLB_WIRED 1	46	#define TLB_WIRED 1
48	#define TLB_KSTACK_WIRED_INDEX 0	47	#define TLB_KSTACK_WIRED_INDEX 0
49		48
50	#define TLB_PAGE_MASK_16K (0x3<<13)	49	#define TLB_PAGE_MASK_16K (0x3<<13)
51		50
52	#define PAGE_UNCACHED 2	51	#define PAGE_UNCACHED 2
53	#define PAGE_CACHEABLE_EXC_WRITE 5	52	#define PAGE_CACHEABLE_EXC_WRITE 5
54		53
55	typedef union entry_lo entry_lo_t;	-
56	typedef union entry_hi entry_hi_t;	-
57	typedef union page_mask page_mask_t;	-
58	typedef union index tlb_index_t;	54	typedef union {
59		-
60	union entry_lo {	-
61	struct {	55	struct {
62	#ifdef BIG_ENDIAN	56	#ifdef BIG_ENDIAN
63	unsigned : 2; /* zero */	57	unsigned : 2; /* zero */
64	unsigned pfn : 24; /* frame number */	58	unsigned pfn : 24; /* frame number */
65	unsigned c : 3; /* cache coherency attribute */	59	unsigned c : 3; /* cache coherency attribute */
66	unsigned d : 1; /* dirty/write-protect bit */	60	unsigned d : 1; /* dirty/write-protect bit */
67	unsigned v : 1; /* valid bit */	61	unsigned v : 1; /* valid bit */
68	unsigned g : 1; /* global bit */	62	unsigned g : 1; /* global bit */
69	#else	63	#else
70	unsigned g : 1; /* global bit */	64	unsigned g : 1; /* global bit */
71	unsigned v : 1; /* valid bit */	65	unsigned v : 1; /* valid bit */
72	unsigned d : 1; /* dirty/write-protect bit */	66	unsigned d : 1; /* dirty/write-protect bit */
73	unsigned c : 3; /* cache coherency attribute */	67	unsigned c : 3; /* cache coherency attribute */
74	unsigned pfn : 24; /* frame number */	68	unsigned pfn : 24; /* frame number */
75	unsigned : 2; /* zero */	69	unsigned : 2; /* zero */
76	#endif	70	#endif
77	} __attribute__ ((packed));	71	} __attribute__ ((packed));
78	uint32_t value;	72	uint32_t value;
79	};	-
80		-
81	/** Page Table Entry. */	-
82	struct pte {	73	} entry_lo_t;
83	unsigned g : 1; /*< Global bit. /	-
84	unsigned p : 1; /*< Present bit. /	-
85	unsigned d : 1; /*< Dirty bit. /	-
86	unsigned cacheable : 1; /*< Cacheable bit. /	-
87	unsigned : 1; /*< Unused. /	-
88	unsigned soft_valid : 1; /*< Valid content even if not present. /	-
89	unsigned pfn : 24; /*< Physical frame number. /	-
90	unsigned w : 1; /*< Page writable bit. /	-
91	unsigned a : 1; /*< Accessed bit. /	-
92	};	-
93		74
94	union entry_hi {	75	typedef union {
95	struct {	76	struct {
96	#ifdef BIG_ENDIAN	77	#ifdef BIG_ENDIAN
97	unsigned vpn2 : 19;	78	unsigned vpn2 : 19;
98	unsigned : 5;	79	unsigned : 5;
99	unsigned asid : 8;	80	unsigned asid : 8;
100	#else	81	#else
101	unsigned asid : 8;	82	unsigned asid : 8;
102	unsigned : 5;	83	unsigned : 5;
103	unsigned vpn2 : 19;	84	unsigned vpn2 : 19;
104	#endif	85	#endif
105	} __attribute__ ((packed));	86	} __attribute__ ((packed));
106	uint32_t value;	87	uint32_t value;
107	};	88	} entry_hi_t;
108		89
109	union page_mask {	90	typedef union {
110	struct {	91	struct {
111	#ifdef BIG_ENDIAN	92	#ifdef BIG_ENDIAN
112	unsigned : 7;	93	unsigned : 7;
113	unsigned mask : 12;	94	unsigned mask : 12;
114	unsigned : 13;	95	unsigned : 13;
115	#else	96	#else
116	unsigned : 13;	97	unsigned : 13;
117	unsigned mask : 12;	98	unsigned mask : 12;
118	unsigned : 7;	99	unsigned : 7;
119	#endif	100	#endif
120	} __attribute__ ((packed));	101	} __attribute__ ((packed));
121	uint32_t value;	102	uint32_t value;
122	};	103	} page_mask_t;
123		104
124	union index {	105	typedef union {
125	struct {	106	struct {
126	#ifdef BIG_ENDIAN	107	#ifdef BIG_ENDIAN
127	unsigned p : 1;	108	unsigned p : 1;
128	unsigned : 27;	109	unsigned : 27;
129	unsigned index : 4;	110	unsigned index : 4;
130	#else	111	#else
131	unsigned index : 4;	112	unsigned index : 4;
132	unsigned : 27;	113	unsigned : 27;
133	unsigned p : 1;	114	unsigned p : 1;
134	#endif	115	#endif
135	} __attribute__ ((packed));	116	} __attribute__ ((packed));
136	uint32_t value;	117	uint32_t value;
137	};	118	} tlb_index_t;
138		119
139	/** Probe TLB for Matching Entry	120	/** Probe TLB for Matching Entry
140	*	121	*
141	* Probe TLB for Matching Entry.	122	* Probe TLB for Matching Entry.
142	*/	123	*/
143	static inline void tlbp(void)	124	static inline void tlbp(void)
144	{	125	{
145	asm volatile ("tlbp\n\t");	126	asm volatile ("tlbp\n\t");
146	}	127	}
147		128
148		129
149	/** Read Indexed TLB Entry	130	/** Read Indexed TLB Entry
150	*	131	*
151	* Read Indexed TLB Entry.	132	* Read Indexed TLB Entry.
152	*/	133	*/
153	static inline void tlbr(void)	134	static inline void tlbr(void)
154	{	135	{
155	asm volatile ("tlbr\n\t");	136	asm volatile ("tlbr\n\t");
156	}	137	}
157		138
158	/** Write Indexed TLB Entry	139	/** Write Indexed TLB Entry
159	*	140	*
160	* Write Indexed TLB Entry.	141	* Write Indexed TLB Entry.
161	*/	142	*/
162	static inline void tlbwi(void)	143	static inline void tlbwi(void)
163	{	144	{
164	asm volatile ("tlbwi\n\t");	145	asm volatile ("tlbwi\n\t");
165	}	146	}
166		147
167	/** Write Random TLB Entry	148	/** Write Random TLB Entry
168	*	149	*
169	* Write Random TLB Entry.	150	* Write Random TLB Entry.
170	*/	151	*/
171	static inline void tlbwr(void)	152	static inline void tlbwr(void)
172	{	153	{
173	asm volatile ("tlbwr\n\t");	154	asm volatile ("tlbwr\n\t");
174	}	155	}
175		156
176	#define tlb_invalidate(asid) tlb_invalidate_asid(asid)	157	#define tlb_invalidate(asid) tlb_invalidate_asid(asid)
177		158
178	extern void tlb_invalid(istate_t *istate);	159	extern void tlb_invalid(istate_t *istate);
179	extern void tlb_refill(istate_t *istate);	160	extern void tlb_refill(istate_t *istate);
180	extern void tlb_modified(istate_t *istate);	161	extern void tlb_modified(istate_t *istate);
181		162
182	#endif	163	#endif
183		164
184	/** @}	165	/** @}
185	*/	166	*/
186		167

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(root)/trunk/kernel/arch/mips32/include/mm/tlb.h – Rev 2082 → 2089