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#include <arch/mm/page.h>
30
#include <arch/mm/page.h>
31
#include <arch/mm/asid.h>
31
#include <arch/mm/asid.h>
32
#include <mm/asid.h>
32
#include <mm/asid.h>
33
 
33
 
34
#define RR_MASK (0xFFFFFFFF00000002)
34
#define RR_MASK (0xFFFFFFFF00000002)
35
#define RID_SHIFT 8
35
#define RID_SHIFT	8
36
#define PS_SHIFT 2
36
#define PS_SHIFT	2
37
 
-
 
38
#define KERNEL_TRANSLATION_I  0x0010000000000661
-
 
39
#define KERNEL_TRANSLATION_D  0x0010000000000661
-
 
40
#define KERNEL_TRANSLATION_VIO 0x0010000000000671
-
 
41
#define KERNEL_TRANSLATION_IO 0x00100FFFFC000671 
-
 
42
#define KERNEL_TRANSLATION_FW 0x00100000F0000671 
-
 
43
 
-
 
44
 
37
 
-
 
38
#define KERNEL_TRANSLATION_I	0x0010000000000661
-
 
39
#define KERNEL_TRANSLATION_D	0x0010000000000661
-
 
40
#define KERNEL_TRANSLATION_VIO	0x0010000000000671
-
 
41
#define KERNEL_TRANSLATION_IO	0x00100FFFFC000671 
-
 
42
#define KERNEL_TRANSLATION_FW	0x00100000F0000671 
45
 
43
 
46
.section K_TEXT_START, "ax"
44
.section K_TEXT_START, "ax"
47
 
45
 
48
.global kernel_image_start
46
.global kernel_image_start
49
 
47
 
50
stack0:
48
stack0:
51
kernel_image_start:
49
kernel_image_start:
52
	.auto
50
	.auto
53
 
51
 
54
#identifi self(CPU) in OS structures by ID / EID
52
	# Identify self(CPU) in OS structures by ID / EID
55
	mov r9=cr64
-
 
56
	mov r10=1
-
 
57
	movl r12=0xffffffff
-
 
58
	movl r8=cpu_by_id_eid_list
-
 
59
	and r8=r8,r12
-
 
60
	shr r9=r9,16
-
 
61
	add r8=r8,r9
-
 
62
	st1 [r8]=r10
-
 
63
 
-
 
64
 
53
 
-
 
54
	mov r9 = cr64
-
 
55
	mov r10 = 1
-
 
56
	movl r12 = 0xffffffff
-
 
57
	movl r8 = cpu_by_id_eid_list
-
 
58
	and r8 = r8, r12
-
 
59
	shr r9 = r9, 16
-
 
60
	add r8 = r8, r9
-
 
61
	st1 [r8] = r10
65
 
62
 
66
	mov psr.l = r0
63
	mov psr.l = r0
67
	srlz.i
64
	srlz.i
68
	srlz.d
65
	srlz.d
69
 
66
 
70
	# Fill TR.i and TR.d using Region Register #VRN_KERNEL
67
	# Fill TR.i and TR.d using Region Register #VRN_KERNEL
71
 
68
 
72
 
-
 
73
	movl r8 = (VRN_KERNEL << VRN_SHIFT)
69
	movl r8 = (VRN_KERNEL << VRN_SHIFT)
74
	mov r9 = rr[r8]
70
	mov r9 = rr[r8]
75
 
71
 
76
 
-
 
77
	movl r10 = (RR_MASK)
72
	movl r10 = (RR_MASK)
78
	and r9 = r10, r9
73
	and r9 = r10, r9
79
	movl r10 = ((RID_KERNEL << RID_SHIFT) | (KERNEL_PAGE_WIDTH << PS_SHIFT))
74
	movl r10 = ((RID_KERNEL << RID_SHIFT) | (KERNEL_PAGE_WIDTH << PS_SHIFT))
80
	or  r9 = r10, r9
75
	or  r9 = r10, r9
81
 
76
 
82
 
-
 
83
	mov rr[r8] = r9
77
	mov rr[r8] = r9
84
 
78
 
85
 
-
 
86
 
-
 
87
	movl r8 = (VRN_KERNEL << VRN_SHIFT)
79
	movl r8 = (VRN_KERNEL << VRN_SHIFT)
88
	mov cr.ifa = r8
80
	mov cr.ifa = r8
89
 
81
 
90
	
-
 
91
	mov r11 = cr.itir ;;
82
	mov r11 = cr.itir ;;
92
	movl r10 = (KERNEL_PAGE_WIDTH << PS_SHIFT);;
83
	movl r10 = (KERNEL_PAGE_WIDTH << PS_SHIFT);;
93
	or r10 =r10 , r11  ;;
84
	or r10 = r10, r11 ;;
94
	mov cr.itir = r10;;
85
	mov cr.itir = r10;;
95
 
86
 
96
	
-
 
97
	movl r10 = (KERNEL_TRANSLATION_I)
87
	movl r10 = (KERNEL_TRANSLATION_I)
98
	itr.i itr[r0] = r10
88
	itr.i itr[r0] = r10
99
 
-
 
100
	
-
 
101
	movl r10 = (KERNEL_TRANSLATION_D)
89
	movl r10 = (KERNEL_TRANSLATION_D)
102
	itr.d dtr[r0] = r10
90
	itr.d dtr[r0] = r10
103
 
91
 
104
 
-
 
105
	movl r7 = 1
92
	movl r7 = 1
106
	movl r8 = (VRN_KERNEL << VRN_SHIFT) | VIO_OFFSET
93
	movl r8 = (VRN_KERNEL << VRN_SHIFT) | VIO_OFFSET
107
	mov cr.ifa = r8
94
	mov cr.ifa = r8
108
	movl r10 = (KERNEL_TRANSLATION_VIO)
95
	movl r10 = (KERNEL_TRANSLATION_VIO)
109
	itr.d dtr[r7] = r10
96
	itr.d dtr[r7] = r10
110
 
97
 
111
 
-
 
112
	mov r11 = cr.itir ;;
98
	mov r11 = cr.itir ;;
113
	movl r10 = ~0xfc;;
99
	movl r10 = ~0xfc;;
114
	and r10 =r10 , r11  ;;
100
	and r10 = r10, r11 ;;
115
	movl r11 = (IO_PAGE_WIDTH << PS_SHIFT);;
101
	movl r11 = (IO_PAGE_WIDTH << PS_SHIFT);;
116
	or r10 =r10 , r11  ;;
102
	or r10 = r10, r11 ;;
117
	mov cr.itir = r10;;
103
	mov cr.itir = r10;;
118
 
104
 
119
 
-
 
120
	movl r7 = 2
105
	movl r7 = 2
121
	movl r8 = (VRN_KERNEL << VRN_SHIFT) | IO_OFFSET
106
	movl r8 = (VRN_KERNEL << VRN_SHIFT) | IO_OFFSET
122
	mov cr.ifa = r8
107
	mov cr.ifa = r8
123
	movl r10 = (KERNEL_TRANSLATION_IO)
108
	movl r10 = (KERNEL_TRANSLATION_IO)
124
	itr.d dtr[r7] = r10
109
	itr.d dtr[r7] = r10
125
 
110
 
-
 
111
	# Setup mapping for fimware arrea (also SAPIC)
126
 
112
 
127
#setup mapping for fimware arrea (also SAPIC)
-
 
128
	mov r11 = cr.itir ;;
113
	mov r11 = cr.itir ;;
129
	movl r10 = ~0xfc;;
114
	movl r10 = ~0xfc;;
130
	and r10 =r10 , r11  ;;
115
	and r10 = r10, r11 ;;
131
	movl r11 = (FW_PAGE_WIDTH << PS_SHIFT);;
116
	movl r11 = (FW_PAGE_WIDTH << PS_SHIFT);;
132
	or r10 =r10 , r11  ;;
117
	or r10 = r10, r11 ;;
133
	mov cr.itir = r10;;
118
	mov cr.itir = r10;;
134
 
119
 
135
 
-
 
136
	movl r7 = 3
120
	movl r7 = 3
137
	movl r8 = (VRN_KERNEL << VRN_SHIFT) | FW_OFFSET
121
	movl r8 = (VRN_KERNEL << VRN_SHIFT) | FW_OFFSET
138
	mov cr.ifa = r8
122
	mov cr.ifa = r8
139
	movl r10 = (KERNEL_TRANSLATION_FW)
123
	movl r10 = (KERNEL_TRANSLATION_FW)
140
	itr.d dtr[r7] = r10
124
	itr.d dtr[r7] = r10
141
 
125
 
-
 
126
	# Initialize PSR
142
 
127
 
143
 
-
 
144
 
-
 
145
 
-
 
146
	# initialize PSR
-
 
147
	movl r10 = (PSR_DT_MASK | PSR_RT_MASK | PSR_IT_MASK | PSR_IC_MASK)  /* Enable paging */
128
	movl r10 = (PSR_DT_MASK | PSR_RT_MASK | PSR_IT_MASK | PSR_IC_MASK)  /* Enable paging */
148
	mov r9 = psr
129
	mov r9 = psr
-
 
130
 
149
	or r10 = r10, r9
131
	or r10 = r10, r9
150
	mov cr.ipsr = r10
132
	mov cr.ipsr = r10
151
	mov cr.ifs = r0
133
	mov cr.ifs = r0
152
	movl r8 = paging_start
134
	movl r8 = paging_start
153
	mov cr.iip = r8
135
	mov cr.iip = r8
154
	srlz.d
136
	srlz.d
155
	srlz.i
137
	srlz.i
156
 
138
 
157
	.explicit
139
	.explicit
-
 
140
 
158
	/*
141
	/*
159
	 * Return From Interupt is the only the way to fill upper half word of PSR.
142
	 * Return From Interupt is the only the way to fill upper half word of PSR.
160
	 */
143
	 */
161
	rfi;;
144
	rfi;;
162
 
145
 
-
 
146
 
163
.global paging_start
147
.global paging_start
164
paging_start:
148
paging_start:
165
 
149
 
166
	/*
150
	/*
167
	 * Now we are paging.
151
	 * Now we are paging.
168
	 */
152
	 */
169
 
153
 
170
	# switch to register bank 1
154
	# Switch to register bank 1
171
	bsw.1
155
	bsw.1
172
 
156
 
173
#Am'I BSP or AP
157
	# Am I BSP or AP?
174
	movl r20=bsp_started;;
158
	movl r20 = bsp_started;;
175
	ld8 r20=[r20];;
159
	ld8 r20 = [r20];;
176
	cmp.eq p3,p2=r20,r0;;
160
	cmp.eq p3, p2 = r20, r0;;
177
 
-
 
178
	
161
	
179
	# initialize register stack
162
	# Initialize register stack
180
	mov ar.rsc = r0
163
	mov ar.rsc = r0
181
	movl r8 = (VRN_KERNEL << VRN_SHIFT) ;;
164
	movl r8 = (VRN_KERNEL << VRN_SHIFT) ;;
182
	mov ar.bspstore = r8
165
	mov ar.bspstore = r8
183
	loadrs
166
	loadrs
184
 
167
 
185
	# initialize memory stack to some sane value
168
	# Initialize memory stack to some sane value
186
	movl r12 = stack0 ;;
169
	movl r12 = stack0 ;;
187
	
-
 
188
	add r12 = -16, r12	/* allocate a scratch area on the stack */
170
	add r12 = -16, r12	/* allocate a scratch area on the stack */
189
 
171
 
190
	# initialize gp (Global Pointer) register
172
	# Initialize gp (Global Pointer) register
191
	movl r20 = (VRN_KERNEL << VRN_SHIFT);;
173
	movl r20 = (VRN_KERNEL << VRN_SHIFT);;
192
	or r20 = r20,r1;;
174
	or r20 = r20,r1;;
193
	movl r1 = _hardcoded_load_address
175
	movl r1 = _hardcoded_load_address
194
	
176
	
195
	/*
177
	/*
Line 214... Line 196...
214
 
196
 
215
(p2)	movl r18 = main_ap ;;
197
(p2)	movl r18 = main_ap ;;
216
(p2)   	mov b1 = r18 ;;
198
(p2)   	mov b1 = r18 ;;
217
(p2)	br.call.sptk.many b0 = b1
199
(p2)	br.call.sptk.many b0 = b1
218
 
200
 
219
#Mark that BSP is on
201
	# Mark that BSP is on
220
	mov r20=1;;
202
	mov r20=1;;
221
	movl r21=bsp_started;;
203
	movl r21=bsp_started;;
222
	st8 [r21]=r20;;
204
	st8 [r21]=r20;;
223
 
205
 
224
 
-
 
225
	br.call.sptk.many b0 = arch_pre_main
206
	br.call.sptk.many b0 = arch_pre_main
226
 
207
 
227
	movl r18 = main_bsp ;;
208
	movl r18 = main_bsp ;;
228
	mov b1 = r18 ;;
209
	mov b1 = r18 ;;
229
	br.call.sptk.many b0 = b1
210
	br.call.sptk.many b0 = b1
230
 
211
 
231
 
-
 
232
0:
212
0:
233
	br 0b
213
	br 0b
234
.align 4096
214
.align 4096
235
 
215
 
236
kernel_image_ap_start:
216
kernel_image_ap_start:
237
	.auto
217
	.auto
-
 
218
 
238
#identifi self(CPU) in OS structures by ID / EID
219
	# Identify self(CPU) in OS structures by ID / EID
-
 
220
 
239
	mov r9=cr64
221
	mov r9 = cr64
240
	mov r10=1
222
	mov r10 = 1
241
	movl r12=0xffffffff
223
	movl r12 = 0xffffffff
242
	movl r8=cpu_by_id_eid_list
224
	movl r8 = cpu_by_id_eid_list
243
	and r8=r8,r12
225
	and r8 = r8, r12
244
	shr r9=r9,16
226
	shr r9 = r9, 16
245
	add r8=r8,r9
227
	add r8 = r8, r9
246
	st1 [r8]=r10
228
	st1 [r8] = r10
247
	
229
	
248
#wait for wakeup sychro signal (#3 in cpu_by_id_eid_list)
230
	# Wait for wakeup synchro signal (#3 in cpu_by_id_eid_list)
249
kernel_image_ap_start_loop:
231
kernel_image_ap_start_loop:
250
	movl r11=kernel_image_ap_start_loop
232
	movl r11 = kernel_image_ap_start_loop
251
	and r11=r11,r12
233
	and r11 = r11, r12
252
   	mov b1 = r11 
234
   	mov b1 = r11 
253
 
235
 
254
	ld1 r20=[r8];;
236
	ld1 r20 = [r8];;
255
	movl r21=3;;
237
	movl r21 = 3;;
256
	cmp.eq p2,p3=r20,r21;;
238
	cmp.eq p2, p3 = r20, r21;;
257
(p3)br.call.sptk.many b0 = b1
239
(p3)	br.call.sptk.many b0 = b1
258
 
240
 
259
	movl r11=kernel_image_start
241
	movl r11 = kernel_image_start
260
	and r11=r11,r12
242
	and r11 = r11, r12
261
    mov b1 = r11 
243
	mov b1 = r11 
262
	br.call.sptk.many b0 = b1
244
	br.call.sptk.many b0 = b1
263
 
245
 
264
 
246
 
265
.align 16
247
.align 16
266
.global bsp_started
248
.global bsp_started
267
bsp_started:
249
bsp_started:
268
.space 8
250
.space 8
269
 
251
 
270
 
-
 
271
.align 4096
252
.align 4096
272
.global cpu_by_id_eid_list
253
.global cpu_by_id_eid_list
273
cpu_by_id_eid_list:
254
cpu_by_id_eid_list:
274
.space 65536
255
.space 65536
275
 
256
 
276
 
-