WebSVN – HelenOS – Diff – /trunk/kernel/arch/ia64/src/mm/page.c


/*
 * Copyright (c) 2006 Jakub Jermar
 * Copyright (c) 2006 Jakub Vana
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * - Redistributions of source code must retain the above copyright
 *   notice, this list of conditions and the following disclaimer.
 * - Redistributions in binary form must reproduce the above copyright
 *   notice, this list of conditions and the following disclaimer in the
 *   documentation and/or other materials provided with the distribution.
 * - The name of the author may not be used to endorse or promote products
 *   derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
/** @addtogroup ia64mm 
 * @{
 */
/** @file
 */
 
#include <arch/mm/page.h>
#include <genarch/mm/page_ht.h>
#include <mm/asid.h>
#include <arch/mm/asid.h>
#include <arch/mm/vhpt.h>
#include <arch/types.h>
 
#include <print.h>
#include <mm/page.h>
#include <mm/frame.h>
#include <config.h>
#include <panic.h>
#include <arch/asm.h>
#include <arch/barrier.h>
#include <memstr.h>
 
static void set_environment(void);
 
/** Initialize ia64 virtual address translation subsystem. */
void page_arch_init(void)
{
    page_mapping_operations = &ht_mapping_operations;
    pk_disable();
    set_environment();
}
 
/** Initialize VHPT and region registers. */
void set_environment(void)
{
    region_register rr;
    pta_register pta;  
    int i;
#ifdef CONFIG_VHPT  
    uintptr_t vhpt_base;
#endif
 
    /*
     * First set up kernel region register.
     * This is redundant (see start.S) but we keep it here just for sure.
     */
    rr.word = rr_read(VRN_KERNEL);
    rr.map.ve = 0;                  /* disable VHPT walker */
    rr.map.ps = PAGE_WIDTH;
    rr.map.rid = ASID2RID(ASID_KERNEL, VRN_KERNEL);
    rr_write(VRN_KERNEL, rr.word);
    srlz_i();
    srlz_d();
 
    /*
     * And setup the rest of region register.
     */
    for(i = 0; i < REGION_REGISTERS; i++) {
        /* skip kernel rr */
        if (i == VRN_KERNEL)
            continue;
   
        rr.word = rr_read(i);
        rr.map.ve = 0;      /* disable VHPT walker */
        rr.map.rid = RID_KERNEL;
        rr.map.ps = PAGE_WIDTH;
        rr_write(i, rr.word);
        srlz_i();
        srlz_d();
    }
 
#ifdef CONFIG_VHPT  
    vhpt_base = vhpt_set_up();
#endif
    /*
     * Set up PTA register.
     */
    pta.word = pta_read();
#ifndef CONFIG_VHPT
    pta.map.ve = 0;                   /* disable VHPT walker */
    pta.map.base = 0 >> PTA_BASE_SHIFT;
#else
    pta.map.ve = 1;                   /* enable VHPT walker */
    pta.map.base = vhpt_base >> PTA_BASE_SHIFT;
#endif
    pta.map.vf = 1;                   /* large entry format */
    pta.map.size = VHPT_WIDTH;
    pta_write(pta.word);
    srlz_i();
    srlz_d();
}
 
/** Calculate address of collision chain from VPN and ASID.
 *
 * Interrupts must be disabled.
 *
 * @param page Address of virtual page including VRN bits.
 * @param asid Address space identifier.
 *
 * @return VHPT entry address.
 */
vhpt_entry_t *vhpt_hash(uintptr_t page, asid_t asid)
{
    region_register rr_save, rr;
    index_t vrn;
    rid_t rid;
    vhpt_entry_t *v;
 
    vrn = page >> VRN_SHIFT;
    rid = ASID2RID(asid, vrn);
   
    rr_save.word = rr_read(vrn);
    if (rr_save.map.rid == rid) {
        /*
         * The RID is already in place, compute thash and return.
         */
        v = (vhpt_entry_t *) thash(page);
        return v;
    }
   
    /*
     * The RID must be written to some region register.
     * To speed things up, register indexed by vrn is used.
     */
    rr.word = rr_save.word;
    rr.map.rid = rid;
    rr_write(vrn, rr.word);
    srlz_i();
    v = (vhpt_entry_t *) thash(page);
    rr_write(vrn, rr_save.word);
    srlz_i();
    srlz_d();
 
    return v;
}
 
/** Compare ASID and VPN against PTE.
 *
 * Interrupts must be disabled.
 *
 * @param page Address of virtual page including VRN bits.
 * @param asid Address space identifier.
 *
 * @return True if page and asid match the page and asid of t, false otherwise.
 */
bool vhpt_compare(uintptr_t page, asid_t asid, vhpt_entry_t *v)
{
    region_register rr_save, rr;   
    index_t vrn;
    rid_t rid;
    bool match;
 
    ASSERT(v);
 
    vrn = page >> VRN_SHIFT;
    rid = ASID2RID(asid, vrn);
   
    rr_save.word = rr_read(vrn);
    if (rr_save.map.rid == rid) {
        /*
         * The RID is already in place, compare ttag with t and return.
         */
        return ttag(page) == v->present.tag.tag_word;
    }
   
    /*
     * The RID must be written to some region register.
     * To speed things up, register indexed by vrn is used.
     */
    rr.word = rr_save.word;
    rr.map.rid = rid;
    rr_write(vrn, rr.word);
    srlz_i();
    match = (ttag(page) == v->present.tag.tag_word);
    rr_write(vrn, rr_save.word);
    srlz_i();
    srlz_d();
 
    return match;      
}
 
/** Set up one VHPT entry.
 *
 * @param v VHPT entry to be set up.
 * @param page Virtual address of the page mapped by the entry.
 * @param asid Address space identifier of the address space to which page belongs.
 * @param frame Physical address of the frame to wich page is mapped.
 * @param flags Different flags for the mapping.
 */
void vhpt_set_record(vhpt_entry_t *v, uintptr_t page, asid_t asid, uintptr_t frame, int flags)
{
    region_register rr_save, rr;   
    index_t vrn;
    rid_t rid;
    uint64_t tag;
 
    ASSERT(v);
 
    vrn = page >> VRN_SHIFT;
    rid = ASID2RID(asid, vrn);
   
    /*
     * Compute ttag.
     */
    rr_save.word = rr_read(vrn);
    rr.word = rr_save.word;
    rr.map.rid = rid;
    rr_write(vrn, rr.word);
    srlz_i();
    tag = ttag(page);
    rr_write(vrn, rr_save.word);
    srlz_i();
    srlz_d();
   
    /*
     * Clear the entry.
     */
    v->word[0] = 0;
    v->word[1] = 0;
    v->word[2] = 0;
    v->word[3] = 0;
   
    v->present.p = true;
    v->present.ma = (flags & PAGE_CACHEABLE) ? MA_WRITEBACK : MA_UNCACHEABLE;
    v->present.a = false;   /* not accessed */
    v->present.d = false;   /* not dirty */
    v->present.pl = (flags & PAGE_USER) ? PL_USER : PL_KERNEL;
    v->present.ar = (flags & PAGE_WRITE) ? AR_WRITE : AR_READ;
    v->present.ar |= (flags & PAGE_EXEC) ? AR_EXECUTE : 0;
    v->present.ppn = frame >> PPN_SHIFT;
    v->present.ed = false;  /* exception not deffered */
    v->present.ps = PAGE_WIDTH;
    v->present.key = 0;
    v->present.tag.tag_word = tag;
}
 
/** @}
 */
 

Rev 2071	Rev 2089
1	/*	1	/*
2	* Copyright (c) 2006 Jakub Jermar	2	* Copyright (c) 2006 Jakub Jermar
3	* Copyright (c) 2006 Jakub Vana	3	* Copyright (c) 2006 Jakub Vana
4	* All rights reserved.	4	* All rights reserved.
5	*	5	*
6	* Redistribution and use in source and binary forms, with or without	6	* Redistribution and use in source and binary forms, with or without
7	* modification, are permitted provided that the following conditions	7	* modification, are permitted provided that the following conditions
8	* are met:	8	* are met:
9	*	9	*
10	* - Redistributions of source code must retain the above copyright	10	* - Redistributions of source code must retain the above copyright
11	* notice, this list of conditions and the following disclaimer.	11	* notice, this list of conditions and the following disclaimer.
12	* - Redistributions in binary form must reproduce the above copyright	12	* - Redistributions in binary form must reproduce the above copyright
13	* notice, this list of conditions and the following disclaimer in the	13	* notice, this list of conditions and the following disclaimer in the
14	* documentation and/or other materials provided with the distribution.	14	* documentation and/or other materials provided with the distribution.
15	* - The name of the author may not be used to endorse or promote products	15	* - The name of the author may not be used to endorse or promote products
16	* derived from this software without specific prior written permission.	16	* derived from this software without specific prior written permission.
17	*	17	*
18	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	18	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	19	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	20	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	21	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	22	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	23	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	24	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	25	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	26	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	27	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28	*/	28	*/
29		29
30	/** @addtogroup ia64mm	30	/** @addtogroup ia64mm
31	* @{	31	* @{
32	*/	32	*/
33	/** @file	33	/** @file
34	*/	34	*/
35		35
36	#include <arch/mm/page.h>	36	#include <arch/mm/page.h>
37	#include <genarch/mm/page_ht.h>	37	#include <genarch/mm/page_ht.h>
38	#include <mm/asid.h>	38	#include <mm/asid.h>
39	#include <arch/mm/asid.h>	39	#include <arch/mm/asid.h>
40	#include <arch/mm/vhpt.h>	40	#include <arch/mm/vhpt.h>
41	#include <arch/types.h>	41	#include <arch/types.h>
42	#include <typedefs.h>	-
43	#include <print.h>	42	#include <print.h>
44	#include <mm/page.h>	43	#include <mm/page.h>
45	#include <mm/frame.h>	44	#include <mm/frame.h>
46	#include <config.h>	45	#include <config.h>
47	#include <panic.h>	46	#include <panic.h>
48	#include <arch/asm.h>	47	#include <arch/asm.h>
49	#include <arch/barrier.h>	48	#include <arch/barrier.h>
50	#include <memstr.h>	49	#include <memstr.h>
51		50
52	static void set_environment(void);	51	static void set_environment(void);
53		52
54	/** Initialize ia64 virtual address translation subsystem. */	53	/** Initialize ia64 virtual address translation subsystem. */
55	void page_arch_init(void)	54	void page_arch_init(void)
56	{	55	{
57	page_mapping_operations = &ht_mapping_operations;	56	page_mapping_operations = &ht_mapping_operations;
58	pk_disable();	57	pk_disable();
59	set_environment();	58	set_environment();
60	}	59	}
61		60
62	/** Initialize VHPT and region registers. */	61	/** Initialize VHPT and region registers. */
63	void set_environment(void)	62	void set_environment(void)
64	{	63	{
65	region_register rr;	64	region_register rr;
66	pta_register pta;	65	pta_register pta;
67	int i;	66	int i;
68	#ifdef CONFIG_VHPT	67	#ifdef CONFIG_VHPT
69	uintptr_t vhpt_base;	68	uintptr_t vhpt_base;
70	#endif	69	#endif
71		70
72	/*	71	/*
73	* First set up kernel region register.	72	* First set up kernel region register.
74	* This is redundant (see start.S) but we keep it here just for sure.	73	* This is redundant (see start.S) but we keep it here just for sure.
75	*/	74	*/
76	rr.word = rr_read(VRN_KERNEL);	75	rr.word = rr_read(VRN_KERNEL);
77	rr.map.ve = 0; /* disable VHPT walker */	76	rr.map.ve = 0; /* disable VHPT walker */
78	rr.map.ps = PAGE_WIDTH;	77	rr.map.ps = PAGE_WIDTH;
79	rr.map.rid = ASID2RID(ASID_KERNEL, VRN_KERNEL);	78	rr.map.rid = ASID2RID(ASID_KERNEL, VRN_KERNEL);
80	rr_write(VRN_KERNEL, rr.word);	79	rr_write(VRN_KERNEL, rr.word);
81	srlz_i();	80	srlz_i();
82	srlz_d();	81	srlz_d();
83		82
84	/*	83	/*
85	* And setup the rest of region register.	84	* And setup the rest of region register.
86	*/	85	*/
87	for(i = 0; i < REGION_REGISTERS; i++) {	86	for(i = 0; i < REGION_REGISTERS; i++) {
88	/* skip kernel rr */	87	/* skip kernel rr */
89	if (i == VRN_KERNEL)	88	if (i == VRN_KERNEL)
90	continue;	89	continue;
91		90
92	rr.word = rr_read(i);	91	rr.word = rr_read(i);
93	rr.map.ve = 0; /* disable VHPT walker */	92	rr.map.ve = 0; /* disable VHPT walker */
94	rr.map.rid = RID_KERNEL;	93	rr.map.rid = RID_KERNEL;
95	rr.map.ps = PAGE_WIDTH;	94	rr.map.ps = PAGE_WIDTH;
96	rr_write(i, rr.word);	95	rr_write(i, rr.word);
97	srlz_i();	96	srlz_i();
98	srlz_d();	97	srlz_d();
99	}	98	}
100		99
101	#ifdef CONFIG_VHPT	100	#ifdef CONFIG_VHPT
102	vhpt_base = vhpt_set_up();	101	vhpt_base = vhpt_set_up();
103	#endif	102	#endif
104	/*	103	/*
105	* Set up PTA register.	104	* Set up PTA register.
106	*/	105	*/
107	pta.word = pta_read();	106	pta.word = pta_read();
108	#ifndef CONFIG_VHPT	107	#ifndef CONFIG_VHPT
109	pta.map.ve = 0; /* disable VHPT walker */	108	pta.map.ve = 0; /* disable VHPT walker */
110	pta.map.base = 0 >> PTA_BASE_SHIFT;	109	pta.map.base = 0 >> PTA_BASE_SHIFT;
111	#else	110	#else
112	pta.map.ve = 1; /* enable VHPT walker */	111	pta.map.ve = 1; /* enable VHPT walker */
113	pta.map.base = vhpt_base >> PTA_BASE_SHIFT;	112	pta.map.base = vhpt_base >> PTA_BASE_SHIFT;
114	#endif	113	#endif
115	pta.map.vf = 1; /* large entry format */	114	pta.map.vf = 1; /* large entry format */
116	pta.map.size = VHPT_WIDTH;	115	pta.map.size = VHPT_WIDTH;
117	pta_write(pta.word);	116	pta_write(pta.word);
118	srlz_i();	117	srlz_i();
119	srlz_d();	118	srlz_d();
120	}	119	}
121		120
122	/** Calculate address of collision chain from VPN and ASID.	121	/** Calculate address of collision chain from VPN and ASID.
123	*	122	*
124	* Interrupts must be disabled.	123	* Interrupts must be disabled.
125	*	124	*
126	* @param page Address of virtual page including VRN bits.	125	* @param page Address of virtual page including VRN bits.
127	* @param asid Address space identifier.	126	* @param asid Address space identifier.
128	*	127	*
129	* @return VHPT entry address.	128	* @return VHPT entry address.
130	*/	129	*/
131	vhpt_entry_t *vhpt_hash(uintptr_t page, asid_t asid)	130	vhpt_entry_t *vhpt_hash(uintptr_t page, asid_t asid)
132	{	131	{
133	region_register rr_save, rr;	132	region_register rr_save, rr;
134	index_t vrn;	133	index_t vrn;
135	rid_t rid;	134	rid_t rid;
136	vhpt_entry_t *v;	135	vhpt_entry_t *v;
137		136
138	vrn = page >> VRN_SHIFT;	137	vrn = page >> VRN_SHIFT;
139	rid = ASID2RID(asid, vrn);	138	rid = ASID2RID(asid, vrn);
140		139
141	rr_save.word = rr_read(vrn);	140	rr_save.word = rr_read(vrn);
142	if (rr_save.map.rid == rid) {	141	if (rr_save.map.rid == rid) {
143	/*	142	/*
144	* The RID is already in place, compute thash and return.	143	* The RID is already in place, compute thash and return.
145	*/	144	*/
146	v = (vhpt_entry_t *) thash(page);	145	v = (vhpt_entry_t *) thash(page);
147	return v;	146	return v;
148	}	147	}
149		148
150	/*	149	/*
151	* The RID must be written to some region register.	150	* The RID must be written to some region register.
152	* To speed things up, register indexed by vrn is used.	151	* To speed things up, register indexed by vrn is used.
153	*/	152	*/
154	rr.word = rr_save.word;	153	rr.word = rr_save.word;
155	rr.map.rid = rid;	154	rr.map.rid = rid;
156	rr_write(vrn, rr.word);	155	rr_write(vrn, rr.word);
157	srlz_i();	156	srlz_i();
158	v = (vhpt_entry_t *) thash(page);	157	v = (vhpt_entry_t *) thash(page);
159	rr_write(vrn, rr_save.word);	158	rr_write(vrn, rr_save.word);
160	srlz_i();	159	srlz_i();
161	srlz_d();	160	srlz_d();
162		161
163	return v;	162	return v;
164	}	163	}
165		164
166	/** Compare ASID and VPN against PTE.	165	/** Compare ASID and VPN against PTE.
167	*	166	*
168	* Interrupts must be disabled.	167	* Interrupts must be disabled.
169	*	168	*
170	* @param page Address of virtual page including VRN bits.	169	* @param page Address of virtual page including VRN bits.
171	* @param asid Address space identifier.	170	* @param asid Address space identifier.
172	*	171	*
173	* @return True if page and asid match the page and asid of t, false otherwise.	172	* @return True if page and asid match the page and asid of t, false otherwise.
174	*/	173	*/
175	bool vhpt_compare(uintptr_t page, asid_t asid, vhpt_entry_t *v)	174	bool vhpt_compare(uintptr_t page, asid_t asid, vhpt_entry_t *v)
176	{	175	{
177	region_register rr_save, rr;	176	region_register rr_save, rr;
178	index_t vrn;	177	index_t vrn;
179	rid_t rid;	178	rid_t rid;
180	bool match;	179	bool match;
181		180
182	ASSERT(v);	181	ASSERT(v);
183		182
184	vrn = page >> VRN_SHIFT;	183	vrn = page >> VRN_SHIFT;
185	rid = ASID2RID(asid, vrn);	184	rid = ASID2RID(asid, vrn);
186		185
187	rr_save.word = rr_read(vrn);	186	rr_save.word = rr_read(vrn);
188	if (rr_save.map.rid == rid) {	187	if (rr_save.map.rid == rid) {
189	/*	188	/*
190	* The RID is already in place, compare ttag with t and return.	189	* The RID is already in place, compare ttag with t and return.
191	*/	190	*/
192	return ttag(page) == v->present.tag.tag_word;	191	return ttag(page) == v->present.tag.tag_word;
193	}	192	}
194		193
195	/*	194	/*
196	* The RID must be written to some region register.	195	* The RID must be written to some region register.
197	* To speed things up, register indexed by vrn is used.	196	* To speed things up, register indexed by vrn is used.
198	*/	197	*/
199	rr.word = rr_save.word;	198	rr.word = rr_save.word;
200	rr.map.rid = rid;	199	rr.map.rid = rid;
201	rr_write(vrn, rr.word);	200	rr_write(vrn, rr.word);
202	srlz_i();	201	srlz_i();
203	match = (ttag(page) == v->present.tag.tag_word);	202	match = (ttag(page) == v->present.tag.tag_word);
204	rr_write(vrn, rr_save.word);	203	rr_write(vrn, rr_save.word);
205	srlz_i();	204	srlz_i();
206	srlz_d();	205	srlz_d();
207		206
208	return match;	207	return match;
209	}	208	}
210		209
211	/** Set up one VHPT entry.	210	/** Set up one VHPT entry.
212	*	211	*
213	* @param v VHPT entry to be set up.	212	* @param v VHPT entry to be set up.
214	* @param page Virtual address of the page mapped by the entry.	213	* @param page Virtual address of the page mapped by the entry.
215	* @param asid Address space identifier of the address space to which page belongs.	214	* @param asid Address space identifier of the address space to which page belongs.
216	* @param frame Physical address of the frame to wich page is mapped.	215	* @param frame Physical address of the frame to wich page is mapped.
217	* @param flags Different flags for the mapping.	216	* @param flags Different flags for the mapping.
218	*/	217	*/
219	void vhpt_set_record(vhpt_entry_t *v, uintptr_t page, asid_t asid, uintptr_t frame, int flags)	218	void vhpt_set_record(vhpt_entry_t *v, uintptr_t page, asid_t asid, uintptr_t frame, int flags)
220	{	219	{
221	region_register rr_save, rr;	220	region_register rr_save, rr;
222	index_t vrn;	221	index_t vrn;
223	rid_t rid;	222	rid_t rid;
224	uint64_t tag;	223	uint64_t tag;
225		224
226	ASSERT(v);	225	ASSERT(v);
227		226
228	vrn = page >> VRN_SHIFT;	227	vrn = page >> VRN_SHIFT;
229	rid = ASID2RID(asid, vrn);	228	rid = ASID2RID(asid, vrn);
230		229
231	/*	230	/*
232	* Compute ttag.	231	* Compute ttag.
233	*/	232	*/
234	rr_save.word = rr_read(vrn);	233	rr_save.word = rr_read(vrn);
235	rr.word = rr_save.word;	234	rr.word = rr_save.word;
236	rr.map.rid = rid;	235	rr.map.rid = rid;
237	rr_write(vrn, rr.word);	236	rr_write(vrn, rr.word);
238	srlz_i();	237	srlz_i();
239	tag = ttag(page);	238	tag = ttag(page);
240	rr_write(vrn, rr_save.word);	239	rr_write(vrn, rr_save.word);
241	srlz_i();	240	srlz_i();
242	srlz_d();	241	srlz_d();
243		242
244	/*	243	/*
245	* Clear the entry.	244	* Clear the entry.
246	*/	245	*/
247	v->word[0] = 0;	246	v->word[0] = 0;
248	v->word[1] = 0;	247	v->word[1] = 0;
249	v->word[2] = 0;	248	v->word[2] = 0;
250	v->word[3] = 0;	249	v->word[3] = 0;
251		250
252	v->present.p = true;	251	v->present.p = true;
253	v->present.ma = (flags & PAGE_CACHEABLE) ? MA_WRITEBACK : MA_UNCACHEABLE;	252	v->present.ma = (flags & PAGE_CACHEABLE) ? MA_WRITEBACK : MA_UNCACHEABLE;
254	v->present.a = false; /* not accessed */	253	v->present.a = false; /* not accessed */
255	v->present.d = false; /* not dirty */	254	v->present.d = false; /* not dirty */
256	v->present.pl = (flags & PAGE_USER) ? PL_USER : PL_KERNEL;	255	v->present.pl = (flags & PAGE_USER) ? PL_USER : PL_KERNEL;
257	v->present.ar = (flags & PAGE_WRITE) ? AR_WRITE : AR_READ;	256	v->present.ar = (flags & PAGE_WRITE) ? AR_WRITE : AR_READ;
258	v->present.ar \|= (flags & PAGE_EXEC) ? AR_EXECUTE : 0;	257	v->present.ar \|= (flags & PAGE_EXEC) ? AR_EXECUTE : 0;
259	v->present.ppn = frame >> PPN_SHIFT;	258	v->present.ppn = frame >> PPN_SHIFT;
260	v->present.ed = false; /* exception not deffered */	259	v->present.ed = false; /* exception not deffered */
261	v->present.ps = PAGE_WIDTH;	260	v->present.ps = PAGE_WIDTH;
262	v->present.key = 0;	261	v->present.key = 0;
263	v->present.tag.tag_word = tag;	262	v->present.tag.tag_word = tag;
264	}	263	}
265		264
266	/** @}	265	/** @}
267	*/	266	*/
268		267

Subversion Repositories HelenOS

(root)/trunk/kernel/arch/ia64/src/mm/page.c – Rev 2071 → 2089