WebSVN – HelenOS – Diff – /trunk/kernel/arch/ia64/src/ivt.S



#include <arch/register.h>
#include <arch/mm/page.h>
#include <align.h>
 
#define FRS_TO_SAVE 30
#define STACK_ITEMS		(21 + FRS_TO_SAVE * 2)
#define STACK_FRAME_SIZE	ALIGN_UP((STACK_ITEMS*STACK_ITEM_SIZE) + STACK_SCRATCH_AREA_SIZE, STACK_ALIGNMENT)
 
#if (STACK_ITEMS % 2 == 0)
#	define STACK_FRAME_BIAS	8
#else

	/*
	 * If this is break_instruction handler,
	 * copy input parameters to stack.
	 */
    	mov R_TMP = 0x2c00 ;;
	cmp.eq p6, p5 = R_OFFS, R_TMP ;;
	
	/*
	 * From now on, if this is break_instruction handler, p6 is true and p5
	 * is false. Otherwise p6 is false and p5 is true.
	 * Note that p5 is a preserved predicate register and we make use of it.
	 */
 
(p6)	st8 [r31] = r38, -8 ;;		/* save in6 */
(p6)	st8 [r31] = r37, -8 ;;		/* save in5 */
(p6)	st8 [r31] = r36, -8 ;;		/* save in4 */	
(p6)	st8 [r31] = r35, -8 ;;		/* save in3 */
(p6) 	st8 [r31] = r34, -8 ;;		/* save in2 */
(p6)	st8 [r31] = r33, -8 ;;		/* save in1 */
(p6)	st8 [r31] = r32, -8 ;;		/* save in0 */
(p5)	add r31 = -56, r31 ;;
    
	st8 [r31] = r30, -8 ;;		/* save old stack pointer */ 
	
	st8 [r31] = r29, -8 ;;		/* save predicate registers */
 

	
	mov r27 = ar.rnat
	mov r28 = ar.bspstore ;;
	
	/*
	 * Inspect BSPSTORE to figure out whether it is necessary to switch to
	 * kernel BSPSTORE.
	 */
(p1)	shr.u r30 = r28, VRN_SHIFT ;;
(p1)	cmp.eq p1, p2 = VRN_KERNEL, r30 ;;
	
	/*

	mov R_RET = b0 			/* save b0 belonging to interrupted context */
	br.call.sptk.many b0 = heavyweight_handler_inner
0:	mov b0 = R_RET			/* restore b0 belonging to the interrupted context */
 
    /* 16. RSE switch to interrupted context */
	cover				/* allocate zero size frame (step 1 (from Intel Docs)) */
 
	add r31 = (STACK_SCRATCH_AREA_SIZE + (FRS_TO_SAVE * 2 * 8)), r12 ;;
 
	ld8 r30 = [r31], +8 ;;		/* load ar.bsp */
	ld8 r29 = [r31], +8 ;;   	/* load ar.bspstore */
	ld8 r28 = [r31], +8 ;;   	/* load ar.bspstore_new */
	sub r27 = r30 , r28 ;;		/* calculate loadrs (step 2) */

Rev 2071	Rev 2608
Line 31...	Line 31...
31	#include <arch/register.h>	31	#include <arch/register.h>
32	#include <arch/mm/page.h>	32	#include <arch/mm/page.h>
33	#include <align.h>	33	#include <align.h>
34		34
35	#define FRS_TO_SAVE 30	35	#define FRS_TO_SAVE 30
36	#define STACK_ITEMS (19 + FRS_TO_SAVE*2)	36	#define STACK_ITEMS (21 + FRS_TO_SAVE * 2)
37	#define STACK_FRAME_SIZE ALIGN_UP((STACK_ITEMS*STACK_ITEM_SIZE) + STACK_SCRATCH_AREA_SIZE, STACK_ALIGNMENT)	37	#define STACK_FRAME_SIZE ALIGN_UP((STACK_ITEMS*STACK_ITEM_SIZE) + STACK_SCRATCH_AREA_SIZE, STACK_ALIGNMENT)
38		38
39	#if (STACK_ITEMS % 2 == 0)	39	#if (STACK_ITEMS % 2 == 0)
40	# define STACK_FRAME_BIAS 8	40	# define STACK_FRAME_BIAS 8
41	#else	41	#else
Line 133...	Line 133...
133	/*	133	/*
134	* If this is break_instruction handler,	134	* If this is break_instruction handler,
135	* copy input parameters to stack.	135	* copy input parameters to stack.
136	*/	136	*/
137	mov R_TMP = 0x2c00 ;;	137	mov R_TMP = 0x2c00 ;;
138	cmp.eq p6,p5 = R_OFFS, R_TMP ;;	138	cmp.eq p6, p5 = R_OFFS, R_TMP ;;
139		139
140	/*	140	/*
141	* From now on, if this is break_instruction handler, p6 is true and p5 is false.	141	* From now on, if this is break_instruction handler, p6 is true and p5
142	* Otherwise p6 is false and p5 is true.	142	* is false. Otherwise p6 is false and p5 is true.
143	* Note that p5 is a preserved predicate register and we make use of it.	143	* Note that p5 is a preserved predicate register and we make use of it.
144	*/	144	*/
145		145
-		146	(p6) st8 [r31] = r38, -8 ;; /* save in6 */
-		147	(p6) st8 [r31] = r37, -8 ;; /* save in5 */
146	(p6) st8 [r31] = r36, -8 ;; /* save in4 */	148	(p6) st8 [r31] = r36, -8 ;; /* save in4 */
147	(p6) st8 [r31] = r35, -8 ;; /* save in3 */	149	(p6) st8 [r31] = r35, -8 ;; /* save in3 */
148	(p6) st8 [r31] = r34, -8 ;; /* save in2 */	150	(p6) st8 [r31] = r34, -8 ;; /* save in2 */
149	(p6) st8 [r31] = r33, -8 ;; /* save in1 */	151	(p6) st8 [r31] = r33, -8 ;; /* save in1 */
150	(p6) st8 [r31] = r32, -8 ;; /* save in0 */	152	(p6) st8 [r31] = r32, -8 ;; /* save in0 */
151	(p5) add r31 = -40, r31 ;;	153	(p5) add r31 = -56, r31 ;;
152		154
153	st8 [r31] = r30, -8 ;; /* save old stack pointer */	155	st8 [r31] = r30, -8 ;; /* save old stack pointer */
154		156
155	st8 [r31] = r29, -8 ;; /* save predicate registers */	157	st8 [r31] = r29, -8 ;; /* save predicate registers */
156		158
Line 176...	Line 178...
176		178
177	mov r27 = ar.rnat	179	mov r27 = ar.rnat
178	mov r28 = ar.bspstore ;;	180	mov r28 = ar.bspstore ;;
179		181
180	/*	182	/*
181	* Inspect BSPSTORE to figure out whether it is necessary to switch to kernel BSPSTORE.	183	* Inspect BSPSTORE to figure out whether it is necessary to switch to
-		184	* kernel BSPSTORE.
182	*/	185	*/
183	(p1) shr.u r30 = r28, VRN_SHIFT ;;	186	(p1) shr.u r30 = r28, VRN_SHIFT ;;
184	(p1) cmp.eq p1, p2 = VRN_KERNEL, r30 ;;	187	(p1) cmp.eq p1, p2 = VRN_KERNEL, r30 ;;
185		188
186	/*	189	/*
Line 203...	Line 206...
203	mov R_RET = b0 /* save b0 belonging to interrupted context */	206	mov R_RET = b0 /* save b0 belonging to interrupted context */
204	br.call.sptk.many b0 = heavyweight_handler_inner	207	br.call.sptk.many b0 = heavyweight_handler_inner
205	0: mov b0 = R_RET /* restore b0 belonging to the interrupted context */	208	0: mov b0 = R_RET /* restore b0 belonging to the interrupted context */
206		209
207	/* 16. RSE switch to interrupted context */	210	/* 16. RSE switch to interrupted context */
208	cover /* allocate zerro size frame (step 1 (from Intel Docs)) */	211	cover /* allocate zero size frame (step 1 (from Intel Docs)) */
209		212
210	add r31 = (STACK_SCRATCH_AREA_SIZE+(FRS_TO_SAVE28)), r12 ;;	213	add r31 = (STACK_SCRATCH_AREA_SIZE + (FRS_TO_SAVE * 2 * 8)), r12 ;;
211		214
212	ld8 r30 = [r31], +8 ;; /* load ar.bsp */	215	ld8 r30 = [r31], +8 ;; /* load ar.bsp */
213	ld8 r29 = [r31], +8 ;; /* load ar.bspstore */	216	ld8 r29 = [r31], +8 ;; /* load ar.bspstore */
214	ld8 r28 = [r31], +8 ;; /* load ar.bspstore_new */	217	ld8 r28 = [r31], +8 ;; /* load ar.bspstore_new */
215	sub r27 = r30 , r28 ;; /* calculate loadrs (step 2) */	218	sub r27 = r30 , r28 ;; /* calculate loadrs (step 2) */

Subversion Repositories HelenOS

(root)/trunk/kernel/arch/ia64/src/ivt.S @ 2071 – Rev 2071 → 2608