WebSVN – HelenOS – Diff – /trunk/kernel/arch/ia64/src/ivt.S


#
# Copyright (c) 2005 Jakub Vana
# Copyright (c) 2005 Jakub Jermar
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions
# are met:
#
# - Redistributions of source code must retain the above copyright
#   notice, this list of conditions and the following disclaimer.
# - Redistributions in binary form must reproduce the above copyright
#   notice, this list of conditions and the following disclaimer in the
#   documentation and/or other materials provided with the distribution.
# - The name of the author may not be used to endorse or promote products
#   derived from this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
 
#include <arch/stack.h>
#include <arch/register.h>
#include <arch/mm/page.h>
#include <align.h>
 
#define FRS_TO_SAVE 30
#define STACK_ITEMS		(19 + FRS_TO_SAVE*2)
#define STACK_FRAME_SIZE	ALIGN_UP((STACK_ITEMS*STACK_ITEM_SIZE) + STACK_SCRATCH_AREA_SIZE, STACK_ALIGNMENT)
 
#if (STACK_ITEMS % 2 == 0)
#	define STACK_FRAME_BIAS	8
#else
#	define STACK_FRAME_BIAS 16
#endif
 
/** Partitioning of bank 0 registers. */
#define R_OFFS 		r16
#define R_HANDLER	r17
#define R_RET		r18
#define R_TMP		r19
#define R_KSTACK_BSP	r22	/* keep in sync with before_thread_runs_arch() */
#define R_KSTACK	r23	/* keep in sync with before_thread_runs_arch() */
 
/** Heavyweight interrupt handler
 *
 * This macro roughly follows steps from 1 to 19 described in
 * Intel Itanium Architecture Software Developer's Manual, Chapter 3.4.2.
 *
 * HEAVYWEIGHT_HANDLER macro must cram into 16 bundles (48 instructions).
 * This goal is achieved by using procedure calls after RSE becomes operational.
 *
 * Some steps are skipped (enabling and disabling interrupts).
 *
 * @param offs Offset from the beginning of IVT.
 * @param handler Interrupt handler address.
 */
.macro HEAVYWEIGHT_HANDLER offs, handler=universal_handler
    .org ivt + \offs
	mov R_OFFS = \offs
	movl R_HANDLER = \handler ;;
	br heavyweight_handler
.endm
 
.global heavyweight_handler
heavyweight_handler:
    /* 1. copy interrupt registers into bank 0 */
    
	/*
	 * Note that r24-r31 from bank 0 can be used only as long as PSR.ic = 0.
	 */
	
	/* Set up FPU as in interrupted context. */
	mov r24 = psr
	mov r25 = cr.ipsr 
	mov r26 = PSR_DFH_MASK
	mov r27 = ~PSR_DFH_MASK ;;
	and r26 = r25, r26
	and r24 = r24, r27;;
	or r24 = r24, r26;;
	mov psr.l = r24;;
	srlz.i
	srlz.d;;
 
	mov r24 = cr.iip
	mov r25 = cr.ipsr
	mov r26 = cr.iipa
	mov r27 = cr.isr
	mov r28 = cr.ifa
	
    /* 2. preserve predicate register into bank 0 */
	mov r29 = pr ;;
	
    /* 3. switch to kernel memory stack */
    	mov r30 = cr.ipsr
	shr.u r31 = r12, VRN_SHIFT ;;
 
	shr.u r30 = r30, PSR_CPL_SHIFT ;;
	and r30 = PSR_CPL_MASK_SHIFTED, r30 ;;
 
	/*
	 * Set p3 to true if the interrupted context executed in kernel mode.
	 * Set p4 to false if the interrupted context didn't execute in kernel mode.
	 */
	cmp.eq p3, p4 = r30, r0 ;;
	cmp.eq p1, p2 = r30, r0 ;;	/* remember IPSR setting in p1 and p2 */
 
	/*
	 * Set p3 to true if the stack register references kernel address space.
	 * Set p4 to false if the stack register doesn't reference kernel address space.
	 */
(p3)	cmp.eq p3, p4 = VRN_KERNEL, r31 ;;
	
	/*
	 * Now, p4 is true iff the stack needs to be switched to kernel stack.
	 */
	mov r30 = r12
(p4)	mov r12 = R_KSTACK ;;
	
	add r31 = -STACK_FRAME_BIAS, r12 ;;
	add r12 = -STACK_FRAME_SIZE, r12
 
    /* 4. save registers in bank 0 into memory stack */
 
	/*
	 * If this is break_instruction handler,
	 * copy input parameters to stack.
	 */
    	mov R_TMP = 0x2c00 ;;
	cmp.eq p6,p5 = R_OFFS, R_TMP ;;
	
	/*
	 * From now on, if this is break_instruction handler, p6 is true and p5 is false.
	 * Otherwise p6 is false and p5 is true.
	 * Note that p5 is a preserved predicate register and we make use of it.
	 */
 
(p6)	st8 [r31] = r36, -8 ;;		/* save in4 */	
(p6)	st8 [r31] = r35, -8 ;;		/* save in3 */
(p6) 	st8 [r31] = r34, -8 ;;		/* save in2 */
(p6)	st8 [r31] = r33, -8 ;;		/* save in1 */
(p6)	st8 [r31] = r32, -8 ;;		/* save in0 */
(p5)	add r31 = -40, r31 ;;
    
	st8 [r31] = r30, -8 ;;		/* save old stack pointer */ 
	
	st8 [r31] = r29, -8 ;;		/* save predicate registers */
 
	st8 [r31] = r24, -8 ;;		/* save cr.iip */
	st8 [r31] = r25, -8 ;;		/* save cr.ipsr */
	st8 [r31] = r26, -8 ;;		/* save cr.iipa */
	st8 [r31] = r27, -8 ;;		/* save cr.isr */
	st8 [r31] = r28, -8 ;;		/* save cr.ifa */
 
    /* 5. RSE switch from interrupted context */
	mov r24 = ar.rsc
	mov r25 = ar.pfs
	cover
	mov r26 = cr.ifs
	
	st8 [r31] = r24, -8 ;;		/* save ar.rsc */
	st8 [r31] = r25, -8 ;;		/* save ar.pfs */
	st8 [r31] = r26, -8		/* save ar.ifs */
	
	and r24 = ~(RSC_PL_MASK), r24 ;;
	and r30 = ~(RSC_MODE_MASK), r24 ;;
	mov ar.rsc = r30 ;;		/* update RSE state */
	
	mov r27 = ar.rnat
	mov r28 = ar.bspstore ;;
	
	/*
	 * Inspect BSPSTORE to figure out whether it is necessary to switch to kernel BSPSTORE.
	 */
(p1)	shr.u r30 = r28, VRN_SHIFT ;;
(p1)	cmp.eq p1, p2 = VRN_KERNEL, r30 ;;
	
	/*
	 * If BSPSTORE needs to be switched, p1 is false and p2 is true.
	 */
(p1)	mov r30 = r28
(p2)	mov r30 = R_KSTACK_BSP ;;
(p2)	mov ar.bspstore = r30 ;;
	
	mov r29 = ar.bsp
	
	st8 [r31] = r27, -8 ;;		/* save ar.rnat */
	st8 [r31] = r30, -8 ;;		/* save new value written to ar.bspstore */
	st8 [r31] = r28, -8 ;;		/* save ar.bspstore */
	st8 [r31] = r29, -8 		/* save ar.bsp */
	
	mov ar.rsc = r24		/* restore RSE's setting + kernel privileges */
	
    /* steps 6 - 15 are done by heavyweight_handler_inner() */
	mov R_RET = b0 			/* save b0 belonging to interrupted context */
	br.call.sptk.many b0 = heavyweight_handler_inner
0:	mov b0 = R_RET			/* restore b0 belonging to the interrupted context */
 
    /* 16. RSE switch to interrupted context */
	cover				/* allocate zerro size frame (step 1 (from Intel Docs)) */
 
	add r31 = (STACK_SCRATCH_AREA_SIZE+(FRS_TO_SAVE*2*8)), r12 ;;
 
	ld8 r30 = [r31], +8 ;;		/* load ar.bsp */
	ld8 r29 = [r31], +8 ;;   	/* load ar.bspstore */
	ld8 r28 = [r31], +8 ;;   	/* load ar.bspstore_new */
	sub r27 = r30 , r28 ;;		/* calculate loadrs (step 2) */
	shl r27 = r27, 16
 
	mov r24 = ar.rsc ;;
	and r30 = ~3, r24 ;;
	or  r24 = r30 , r27 ;;     
	mov ar.rsc = r24 ;;		/* place RSE in enforced lazy mode */
 
	loadrs 				/* (step 3) */
 
	ld8 r27 = [r31], +8 ;;		/* load ar.rnat */
	ld8 r26 = [r31], +8 ;;		/* load cr.ifs */
	ld8 r25 = [r31], +8 ;;		/* load ar.pfs */
	ld8 r24 = [r31], +8 ;;		/* load ar.rsc */
 
	mov ar.bspstore = r29 ;;	/* (step 4) */
	mov ar.rnat = r27		/* (step 5) */
 
	mov ar.pfs = r25		/* (step 6) */
	mov cr.ifs = r26	
 
	mov ar.rsc = r24		/* (step 7) */
 
    /* 17. restore interruption state from memory stack */
	ld8 r28 = [r31], +8 ;;		/* load cr.ifa */		
	ld8 r27 = [r31], +8 ;;		/* load cr.isr */
	ld8 r26 = [r31], +8 ;;		/* load cr.iipa */
	ld8 r25 = [r31], +8 ;;		/* load cr.ipsr */
	ld8 r24 = [r31], +8 ;;		/* load cr.iip */
 
	mov cr.iip = r24;;
	mov cr.iipa = r26
	mov cr.isr = r27
	mov cr.ifa = r28
 
	/* Set up FPU as in exception. */
	mov r24 = psr
	mov r26 = PSR_DFH_MASK
	mov r27 = ~PSR_DFH_MASK ;;
	and r25 = r25, r27
	and r24 = r24, r26 ;;
	or r25 = r25, r24;;
	mov cr.ipsr = r25
 
    /* 18. restore predicate registers from memory stack */
	ld8 r29 = [r31], +8 ;;		/* load predicate registers */
	mov pr = r29
	
    /* 19. return from interruption */
    	ld8 r12 = [r31]			/* load stack pointer */ 
	rfi ;;
 
.global heavyweight_handler_inner
heavyweight_handler_inner:
	/*
	 * From this point, the rest of the interrupted context
	 * will be preserved in stacked registers and backing store.
	 */
	alloc loc0 = ar.pfs, 0, 48, 2, 0 ;;
	
	/* bank 0 is going to be shadowed, copy essential data from there */
	mov loc1 = R_RET	/* b0 belonging to interrupted context */
	mov loc2 = R_HANDLER
	mov out0 = R_OFFS
	
	add out1 = STACK_SCRATCH_AREA_SIZE, r12
 
    /* 6. switch to bank 1 and reenable PSR.ic */
	ssm PSR_IC_MASK
	bsw.1 ;;
	srlz.d
	
    /* 7. preserve branch and application registers */
    	mov loc3 = ar.unat
	mov loc4 = ar.lc
	mov loc5 = ar.ec
	mov loc6 = ar.ccv
	mov loc7 = ar.csd
	mov loc8 = ar.ssd
	
	mov loc9 = b0
	mov loc10 = b1
	mov loc11 = b2
	mov loc12 = b3
	mov loc13 = b4
	mov loc14 = b5
	mov loc15 = b6
	mov loc16 = b7
	
    /* 8. preserve general and floating-point registers */
	mov loc17 = r1
	mov loc18 = r2
	mov loc19 = r3
	mov loc20 = r4
	mov loc21 = r5
	mov loc22 = r6
	mov loc23 = r7
(p5)	mov loc24 = r8		/* only if not in break_instruction handler */
	mov loc25 = r9
	mov loc26 = r10
	mov loc27 = r11
	/* skip r12 (stack pointer) */
	mov loc28 = r13
	mov loc29 = r14
	mov loc30 = r15
	mov loc31 = r16
	mov loc32 = r17
	mov loc33 = r18
	mov loc34 = r19
	mov loc35 = r20
	mov loc36 = r21
	mov loc37 = r22
	mov loc38 = r23
	mov loc39 = r24
	mov loc40 = r25
	mov loc41 = r26
	mov loc42 = r27
	mov loc43 = r28
	mov loc44 = r29
	mov loc45 = r30
	mov loc46 = r31
 
	add r24 = 96 + STACK_SCRATCH_AREA_SIZE, r12
	add r25 = 112 + STACK_SCRATCH_AREA_SIZE, r12
	add r26 = 0 + STACK_SCRATCH_AREA_SIZE, r12
	add r27 = 16 + STACK_SCRATCH_AREA_SIZE, r12
	add r28 = 32 + STACK_SCRATCH_AREA_SIZE, r12
	add r29 = 48 + STACK_SCRATCH_AREA_SIZE, r12
	add r30 = 64 + STACK_SCRATCH_AREA_SIZE, r12
	add r31 = 80 + STACK_SCRATCH_AREA_SIZE, r12 ;;
	
	stf.spill [r26] = f2, 0x80
	stf.spill [r27] = f3, 0x80
	stf.spill [r28] = f4, 0x80
	stf.spill [r29] = f5, 0x80
	stf.spill [r30] = f6, 0x80
	stf.spill [r31] = f7, 0x80 ;;
 
	stf.spill [r24] = f8, 0x80
	stf.spill [r25] = f9, 0x80
	stf.spill [r26] = f10, 0x80
	stf.spill [r27] = f11, 0x80
	stf.spill [r28] = f12, 0x80
	stf.spill [r29] = f13, 0x80
	stf.spill [r30] = f14, 0x80
	stf.spill [r31] = f15, 0x80 ;;
 
	stf.spill [r24] = f16, 0x80
	stf.spill [r25] = f17, 0x80
	stf.spill [r26] = f18, 0x80
	stf.spill [r27] = f19, 0x80
	stf.spill [r28] = f20, 0x80
	stf.spill [r29] = f21, 0x80
	stf.spill [r30] = f22, 0x80
	stf.spill [r31] = f23, 0x80 ;;
 
	stf.spill [r24] = f24, 0x80
	stf.spill [r25] = f25, 0x80
	stf.spill [r26] = f26, 0x80
	stf.spill [r27] = f27, 0x80
	stf.spill [r28] = f28, 0x80
	stf.spill [r29] = f29, 0x80
	stf.spill [r30] = f30, 0x80
	stf.spill [r31] = f31, 0x80 ;;
 
	mov loc47 = ar.fpsr	/* preserve floating point status register */
    
    /* 9. skipped (will not enable interrupts) */
	/*
    	 * ssm PSR_I_MASK
	 * ;;
	 * srlz.d
	 */
 
    /* 10. call handler */
    	movl r1 = _hardcoded_load_address
    
    	mov b1 = loc2
	br.call.sptk.many b0 = b1
 
    /* 11. return from handler */
0:
	
    /* 12. skipped (will not disable interrupts) */
	/*
    	 * rsm PSR_I_MASK
	 * ;;
	 * srlz.d
	 */
 
    /* 13. restore general and floating-point registers */
	add r24 = 96 + STACK_SCRATCH_AREA_SIZE, r12
	add r25 = 112 + STACK_SCRATCH_AREA_SIZE, r12
	add r26 = 0 + STACK_SCRATCH_AREA_SIZE, r12
	add r27 = 16 + STACK_SCRATCH_AREA_SIZE, r12
	add r28 = 32 + STACK_SCRATCH_AREA_SIZE, r12
	add r29 = 48 + STACK_SCRATCH_AREA_SIZE, r12
	add r30 = 64 + STACK_SCRATCH_AREA_SIZE, r12
	add r31 = 80 + STACK_SCRATCH_AREA_SIZE, r12 ;;
 
	ldf.fill f2 = [r26], 0x80
	ldf.fill f3 = [r27], 0x80
	ldf.fill f4 = [r28], 0x80
	ldf.fill f5 = [r29], 0x80
	ldf.fill f6 = [r30], 0x80
	ldf.fill f7 = [r31], 0x80 ;;
 
	ldf.fill f8 = [r24], 0x80
	ldf.fill f9 = [r25], 0x80
	ldf.fill f10 = [r26], 0x80
	ldf.fill f11 = [r27], 0x80
	ldf.fill f12 = [r28], 0x80
	ldf.fill f13 = [r29], 0x80
	ldf.fill f14 = [r30], 0x80
	ldf.fill f15 = [r31], 0x80 ;;
 
	ldf.fill f16 = [r24], 0x80
	ldf.fill f17 = [r25], 0x80
	ldf.fill f18 = [r26], 0x80
	ldf.fill f19 = [r27], 0x80
	ldf.fill f20 = [r28], 0x80
	ldf.fill f21 = [r29], 0x80
	ldf.fill f22 = [r30], 0x80
	ldf.fill f23 = [r31], 0x80 ;;
 
	ldf.fill f24 = [r24], 0x80
	ldf.fill f25 = [r25], 0x80
	ldf.fill f26 = [r26], 0x80
	ldf.fill f27 = [r27], 0x80
	ldf.fill f28 = [r28], 0x80
	ldf.fill f29 = [r29], 0x80
	ldf.fill f30 = [r30], 0x80
	ldf.fill f31 = [r31], 0x80 ;;
	
	mov r1 = loc17
	mov r2 = loc18
	mov r3 = loc19
	mov r4 = loc20
	mov r5 = loc21
	mov r6 = loc22
	mov r7 = loc23
(p5)	mov r8 = loc24		/* only if not in break_instruction handler */
	mov r9 = loc25
	mov r10 = loc26
	mov r11 = loc27
	/* skip r12 (stack pointer) */
	mov r13 = loc28
	mov r14 = loc29
	mov r15 = loc30
	mov r16 = loc31
	mov r17 = loc32
	mov r18 = loc33
	mov r19 = loc34
	mov r20 = loc35
	mov r21 = loc36
	mov r22 = loc37
	mov r23 = loc38
	mov r24 = loc39
	mov r25 = loc40
	mov r26 = loc41 
	mov r27 = loc42
	mov r28 = loc43
	mov r29 = loc44
	mov r30 = loc45
	mov r31 = loc46
 
	mov ar.fpsr = loc47	/* restore floating point status register */
	
    /* 14. restore branch and application registers */
    	mov ar.unat = loc3
	mov ar.lc = loc4
	mov ar.ec = loc5
	mov ar.ccv = loc6
	mov ar.csd = loc7
	mov ar.ssd = loc8
	
	mov b0 = loc9
	mov b1 = loc10
	mov b2 = loc11
	mov b3 = loc12
	mov b4 = loc13
	mov b5 = loc14
	mov b6 = loc15
	mov b7 = loc16
	
    /* 15. disable PSR.ic and switch to bank 0 */
	rsm PSR_IC_MASK
	bsw.0 ;;
	srlz.d
 
	mov R_RET = loc1
	mov ar.pfs = loc0
	br.ret.sptk.many b0
 
.global ivt
.align 32768
ivt:
	HEAVYWEIGHT_HANDLER 0x0000
	HEAVYWEIGHT_HANDLER 0x0400
	HEAVYWEIGHT_HANDLER 0x0800
	HEAVYWEIGHT_HANDLER 0x0c00 alternate_instruction_tlb_fault
	HEAVYWEIGHT_HANDLER 0x1000 alternate_data_tlb_fault
	HEAVYWEIGHT_HANDLER 0x1400 data_nested_tlb_fault
	HEAVYWEIGHT_HANDLER 0x1800
	HEAVYWEIGHT_HANDLER 0x1c00
	HEAVYWEIGHT_HANDLER 0x2000 data_dirty_bit_fault
	HEAVYWEIGHT_HANDLER 0x2400 instruction_access_bit_fault
	HEAVYWEIGHT_HANDLER 0x2800 data_access_bit_fault
	HEAVYWEIGHT_HANDLER 0x2c00 break_instruction
	HEAVYWEIGHT_HANDLER 0x3000 external_interrupt	/* For external interrupt, heavyweight handler is used. */
	HEAVYWEIGHT_HANDLER 0x3400
	HEAVYWEIGHT_HANDLER 0x3800
	HEAVYWEIGHT_HANDLER 0x3c00
	HEAVYWEIGHT_HANDLER 0x4000
	HEAVYWEIGHT_HANDLER 0x4400
	HEAVYWEIGHT_HANDLER 0x4800
	HEAVYWEIGHT_HANDLER 0x4c00
 
	HEAVYWEIGHT_HANDLER 0x5000 page_not_present
	HEAVYWEIGHT_HANDLER 0x5100
	HEAVYWEIGHT_HANDLER 0x5200
	HEAVYWEIGHT_HANDLER 0x5300
	HEAVYWEIGHT_HANDLER 0x5400 general_exception
	HEAVYWEIGHT_HANDLER 0x5500 disabled_fp_register
	HEAVYWEIGHT_HANDLER 0x5600
	HEAVYWEIGHT_HANDLER 0x5700
	HEAVYWEIGHT_HANDLER 0x5800
	HEAVYWEIGHT_HANDLER 0x5900
	HEAVYWEIGHT_HANDLER 0x5a00
	HEAVYWEIGHT_HANDLER 0x5b00
	HEAVYWEIGHT_HANDLER 0x5c00
	HEAVYWEIGHT_HANDLER 0x5d00 
	HEAVYWEIGHT_HANDLER 0x5e00
	HEAVYWEIGHT_HANDLER 0x5f00
	
	HEAVYWEIGHT_HANDLER 0x6000
	HEAVYWEIGHT_HANDLER 0x6100
	HEAVYWEIGHT_HANDLER 0x6200
	HEAVYWEIGHT_HANDLER 0x6300
	HEAVYWEIGHT_HANDLER 0x6400
	HEAVYWEIGHT_HANDLER 0x6500
	HEAVYWEIGHT_HANDLER 0x6600
	HEAVYWEIGHT_HANDLER 0x6700
	HEAVYWEIGHT_HANDLER 0x6800
	HEAVYWEIGHT_HANDLER 0x6900
	HEAVYWEIGHT_HANDLER 0x6a00
	HEAVYWEIGHT_HANDLER 0x6b00
	HEAVYWEIGHT_HANDLER 0x6c00
	HEAVYWEIGHT_HANDLER 0x6d00
	HEAVYWEIGHT_HANDLER 0x6e00
	HEAVYWEIGHT_HANDLER 0x6f00
 
	HEAVYWEIGHT_HANDLER 0x7000
	HEAVYWEIGHT_HANDLER 0x7100
	HEAVYWEIGHT_HANDLER 0x7200
	HEAVYWEIGHT_HANDLER 0x7300
	HEAVYWEIGHT_HANDLER 0x7400
	HEAVYWEIGHT_HANDLER 0x7500
	HEAVYWEIGHT_HANDLER 0x7600
	HEAVYWEIGHT_HANDLER 0x7700
	HEAVYWEIGHT_HANDLER 0x7800
	HEAVYWEIGHT_HANDLER 0x7900
	HEAVYWEIGHT_HANDLER 0x7a00
	HEAVYWEIGHT_HANDLER 0x7b00
	HEAVYWEIGHT_HANDLER 0x7c00
	HEAVYWEIGHT_HANDLER 0x7d00
	HEAVYWEIGHT_HANDLER 0x7e00
	HEAVYWEIGHT_HANDLER 0x7f00
 

Rev 1787	Rev 2071
1	#	1	#
2	# Copyright (C) 2005 Jakub Vana	2	# Copyright (c) 2005 Jakub Vana
3	# Copyright (C) 2005 Jakub Jermar	3	# Copyright (c) 2005 Jakub Jermar
4	# All rights reserved.	4	# All rights reserved.
5	#	5	#
6	# Redistribution and use in source and binary forms, with or without	6	# Redistribution and use in source and binary forms, with or without
7	# modification, are permitted provided that the following conditions	7	# modification, are permitted provided that the following conditions
8	# are met:	8	# are met:
9	#	9	#
10	# - Redistributions of source code must retain the above copyright	10	# - Redistributions of source code must retain the above copyright
11	# notice, this list of conditions and the following disclaimer.	11	# notice, this list of conditions and the following disclaimer.
12	# - Redistributions in binary form must reproduce the above copyright	12	# - Redistributions in binary form must reproduce the above copyright
13	# notice, this list of conditions and the following disclaimer in the	13	# notice, this list of conditions and the following disclaimer in the
14	# documentation and/or other materials provided with the distribution.	14	# documentation and/or other materials provided with the distribution.
15	# - The name of the author may not be used to endorse or promote products	15	# - The name of the author may not be used to endorse or promote products
16	# derived from this software without specific prior written permission.	16	# derived from this software without specific prior written permission.
17	#	17	#
18	# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	18	# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19	# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	19	# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20	# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	20	# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21	# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	21	# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22	# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	22	# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23	# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	23	# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24	# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	24	# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25	# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	25	# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26	# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	26	# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27	# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	27	# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28	#	28	#
29		29
30	#include <arch/stack.h>	30	#include <arch/stack.h>
31	#include <arch/register.h>	31	#include <arch/register.h>
32	#include <arch/mm/page.h>	32	#include <arch/mm/page.h>
33	#include <align.h>	33	#include <align.h>
34		34
35	#define FRS_TO_SAVE 30	35	#define FRS_TO_SAVE 30
36	#define STACK_ITEMS (19 + FRS_TO_SAVE*2)	36	#define STACK_ITEMS (19 + FRS_TO_SAVE*2)
37	#define STACK_FRAME_SIZE ALIGN_UP((STACK_ITEMS*STACK_ITEM_SIZE) + STACK_SCRATCH_AREA_SIZE, STACK_ALIGNMENT)	37	#define STACK_FRAME_SIZE ALIGN_UP((STACK_ITEMS*STACK_ITEM_SIZE) + STACK_SCRATCH_AREA_SIZE, STACK_ALIGNMENT)
38		38
39	#if (STACK_ITEMS % 2 == 0)	39	#if (STACK_ITEMS % 2 == 0)
40	# define STACK_FRAME_BIAS 8	40	# define STACK_FRAME_BIAS 8
41	#else	41	#else
42	# define STACK_FRAME_BIAS 16	42	# define STACK_FRAME_BIAS 16
43	#endif	43	#endif
44		44
45	/** Partitioning of bank 0 registers. */	45	/** Partitioning of bank 0 registers. */
46	#define R_OFFS r16	46	#define R_OFFS r16
47	#define R_HANDLER r17	47	#define R_HANDLER r17
48	#define R_RET r18	48	#define R_RET r18
49	#define R_TMP r19	49	#define R_TMP r19
50	#define R_KSTACK_BSP r22 /* keep in sync with before_thread_runs_arch() */	50	#define R_KSTACK_BSP r22 /* keep in sync with before_thread_runs_arch() */
51	#define R_KSTACK r23 /* keep in sync with before_thread_runs_arch() */	51	#define R_KSTACK r23 /* keep in sync with before_thread_runs_arch() */
52		52
53	/** Heavyweight interrupt handler	53	/** Heavyweight interrupt handler
54	*	54	*
55	* This macro roughly follows steps from 1 to 19 described in	55	* This macro roughly follows steps from 1 to 19 described in
56	* Intel Itanium Architecture Software Developer's Manual, Chapter 3.4.2.	56	* Intel Itanium Architecture Software Developer's Manual, Chapter 3.4.2.
57	*	57	*
58	* HEAVYWEIGHT_HANDLER macro must cram into 16 bundles (48 instructions).	58	* HEAVYWEIGHT_HANDLER macro must cram into 16 bundles (48 instructions).
59	* This goal is achieved by using procedure calls after RSE becomes operational.	59	* This goal is achieved by using procedure calls after RSE becomes operational.
60	*	60	*
61	* Some steps are skipped (enabling and disabling interrupts).	61	* Some steps are skipped (enabling and disabling interrupts).
62	*	62	*
63	* @param offs Offset from the beginning of IVT.	63	* @param offs Offset from the beginning of IVT.
64	* @param handler Interrupt handler address.	64	* @param handler Interrupt handler address.
65	*/	65	*/
66	.macro HEAVYWEIGHT_HANDLER offs, handler=universal_handler	66	.macro HEAVYWEIGHT_HANDLER offs, handler=universal_handler
67	.org ivt + \offs	67	.org ivt + \offs
68	mov R_OFFS = \offs	68	mov R_OFFS = \offs
69	movl R_HANDLER = \handler ;;	69	movl R_HANDLER = \handler ;;
70	br heavyweight_handler	70	br heavyweight_handler
71	.endm	71	.endm
72		72
73	.global heavyweight_handler	73	.global heavyweight_handler
74	heavyweight_handler:	74	heavyweight_handler:
75	/* 1. copy interrupt registers into bank 0 */	75	/* 1. copy interrupt registers into bank 0 */
76		76
77	/*	77	/*
78	* Note that r24-r31 from bank 0 can be used only as long as PSR.ic = 0.	78	* Note that r24-r31 from bank 0 can be used only as long as PSR.ic = 0.
79	*/	79	*/
80		80
81	/* Set up FPU as in interrupted context. */	81	/* Set up FPU as in interrupted context. */
82	mov r24 = psr	82	mov r24 = psr
83	mov r25 = cr.ipsr	83	mov r25 = cr.ipsr
84	mov r26 = PSR_DFH_MASK	84	mov r26 = PSR_DFH_MASK
85	mov r27 = ~PSR_DFH_MASK ;;	85	mov r27 = ~PSR_DFH_MASK ;;
86	and r26 = r25, r26	86	and r26 = r25, r26
87	and r24 = r24, r27;;	87	and r24 = r24, r27;;
88	or r24 = r24, r26;;	88	or r24 = r24, r26;;
89	mov psr.l = r24;;	89	mov psr.l = r24;;
90	srlz.i	90	srlz.i
91	srlz.d;;	91	srlz.d;;
92		92
93	mov r24 = cr.iip	93	mov r24 = cr.iip
94	mov r25 = cr.ipsr	94	mov r25 = cr.ipsr
95	mov r26 = cr.iipa	95	mov r26 = cr.iipa
96	mov r27 = cr.isr	96	mov r27 = cr.isr
97	mov r28 = cr.ifa	97	mov r28 = cr.ifa
98		98
99	/* 2. preserve predicate register into bank 0 */	99	/* 2. preserve predicate register into bank 0 */
100	mov r29 = pr ;;	100	mov r29 = pr ;;
101		101
102	/* 3. switch to kernel memory stack */	102	/* 3. switch to kernel memory stack */
103	mov r30 = cr.ipsr	103	mov r30 = cr.ipsr
104	shr.u r31 = r12, VRN_SHIFT ;;	104	shr.u r31 = r12, VRN_SHIFT ;;
105		105
106	shr.u r30 = r30, PSR_CPL_SHIFT ;;	106	shr.u r30 = r30, PSR_CPL_SHIFT ;;
107	and r30 = PSR_CPL_MASK_SHIFTED, r30 ;;	107	and r30 = PSR_CPL_MASK_SHIFTED, r30 ;;
108		108
109	/*	109	/*
110	* Set p3 to true if the interrupted context executed in kernel mode.	110	* Set p3 to true if the interrupted context executed in kernel mode.
111	* Set p4 to false if the interrupted context didn't execute in kernel mode.	111	* Set p4 to false if the interrupted context didn't execute in kernel mode.
112	*/	112	*/
113	cmp.eq p3, p4 = r30, r0 ;;	113	cmp.eq p3, p4 = r30, r0 ;;
114	cmp.eq p1, p2 = r30, r0 ;; /* remember IPSR setting in p1 and p2 */	114	cmp.eq p1, p2 = r30, r0 ;; /* remember IPSR setting in p1 and p2 */
115		115
116	/*	116	/*
117	* Set p3 to true if the stack register references kernel address space.	117	* Set p3 to true if the stack register references kernel address space.
118	* Set p4 to false if the stack register doesn't reference kernel address space.	118	* Set p4 to false if the stack register doesn't reference kernel address space.
119	*/	119	*/
120	(p3) cmp.eq p3, p4 = VRN_KERNEL, r31 ;;	120	(p3) cmp.eq p3, p4 = VRN_KERNEL, r31 ;;
121		121
122	/*	122	/*
123	* Now, p4 is true iff the stack needs to be switched to kernel stack.	123	* Now, p4 is true iff the stack needs to be switched to kernel stack.
124	*/	124	*/
125	mov r30 = r12	125	mov r30 = r12
126	(p4) mov r12 = R_KSTACK ;;	126	(p4) mov r12 = R_KSTACK ;;
127		127
128	add r31 = -STACK_FRAME_BIAS, r12 ;;	128	add r31 = -STACK_FRAME_BIAS, r12 ;;
129	add r12 = -STACK_FRAME_SIZE, r12	129	add r12 = -STACK_FRAME_SIZE, r12
130		130
131	/* 4. save registers in bank 0 into memory stack */	131	/* 4. save registers in bank 0 into memory stack */
132		132
133	/*	133	/*
134	* If this is break_instruction handler,	134	* If this is break_instruction handler,
135	* copy input parameters to stack.	135	* copy input parameters to stack.
136	*/	136	*/
137	mov R_TMP = 0x2c00 ;;	137	mov R_TMP = 0x2c00 ;;
138	cmp.eq p6,p5 = R_OFFS, R_TMP ;;	138	cmp.eq p6,p5 = R_OFFS, R_TMP ;;
139		139
140	/*	140	/*
141	* From now on, if this is break_instruction handler, p6 is true and p5 is false.	141	* From now on, if this is break_instruction handler, p6 is true and p5 is false.
142	* Otherwise p6 is false and p5 is true.	142	* Otherwise p6 is false and p5 is true.
143	* Note that p5 is a preserved predicate register and we make use of it.	143	* Note that p5 is a preserved predicate register and we make use of it.
144	*/	144	*/
145		145
146	(p6) st8 [r31] = r36, -8 ;; /* save in4 */	146	(p6) st8 [r31] = r36, -8 ;; /* save in4 */
147	(p6) st8 [r31] = r35, -8 ;; /* save in3 */	147	(p6) st8 [r31] = r35, -8 ;; /* save in3 */
148	(p6) st8 [r31] = r34, -8 ;; /* save in2 */	148	(p6) st8 [r31] = r34, -8 ;; /* save in2 */
149	(p6) st8 [r31] = r33, -8 ;; /* save in1 */	149	(p6) st8 [r31] = r33, -8 ;; /* save in1 */
150	(p6) st8 [r31] = r32, -8 ;; /* save in0 */	150	(p6) st8 [r31] = r32, -8 ;; /* save in0 */
151	(p5) add r31 = -40, r31 ;;	151	(p5) add r31 = -40, r31 ;;
152		152
153	st8 [r31] = r30, -8 ;; /* save old stack pointer */	153	st8 [r31] = r30, -8 ;; /* save old stack pointer */
154		154
155	st8 [r31] = r29, -8 ;; /* save predicate registers */	155	st8 [r31] = r29, -8 ;; /* save predicate registers */
156		156
157	st8 [r31] = r24, -8 ;; /* save cr.iip */	157	st8 [r31] = r24, -8 ;; /* save cr.iip */
158	st8 [r31] = r25, -8 ;; /* save cr.ipsr */	158	st8 [r31] = r25, -8 ;; /* save cr.ipsr */
159	st8 [r31] = r26, -8 ;; /* save cr.iipa */	159	st8 [r31] = r26, -8 ;; /* save cr.iipa */
160	st8 [r31] = r27, -8 ;; /* save cr.isr */	160	st8 [r31] = r27, -8 ;; /* save cr.isr */
161	st8 [r31] = r28, -8 ;; /* save cr.ifa */	161	st8 [r31] = r28, -8 ;; /* save cr.ifa */
162		162
163	/* 5. RSE switch from interrupted context */	163	/* 5. RSE switch from interrupted context */
164	mov r24 = ar.rsc	164	mov r24 = ar.rsc
165	mov r25 = ar.pfs	165	mov r25 = ar.pfs
166	cover	166	cover
167	mov r26 = cr.ifs	167	mov r26 = cr.ifs
168		168
169	st8 [r31] = r24, -8 ;; /* save ar.rsc */	169	st8 [r31] = r24, -8 ;; /* save ar.rsc */
170	st8 [r31] = r25, -8 ;; /* save ar.pfs */	170	st8 [r31] = r25, -8 ;; /* save ar.pfs */
171	st8 [r31] = r26, -8 /* save ar.ifs */	171	st8 [r31] = r26, -8 /* save ar.ifs */
172		172
173	and r24 = ~(RSC_PL_MASK), r24 ;;	173	and r24 = ~(RSC_PL_MASK), r24 ;;
174	and r30 = ~(RSC_MODE_MASK), r24 ;;	174	and r30 = ~(RSC_MODE_MASK), r24 ;;
175	mov ar.rsc = r30 ;; /* update RSE state */	175	mov ar.rsc = r30 ;; /* update RSE state */
176		176
177	mov r27 = ar.rnat	177	mov r27 = ar.rnat
178	mov r28 = ar.bspstore ;;	178	mov r28 = ar.bspstore ;;
179		179
180	/*	180	/*
181	* Inspect BSPSTORE to figure out whether it is necessary to switch to kernel BSPSTORE.	181	* Inspect BSPSTORE to figure out whether it is necessary to switch to kernel BSPSTORE.
182	*/	182	*/
183	(p1) shr.u r30 = r28, VRN_SHIFT ;;	183	(p1) shr.u r30 = r28, VRN_SHIFT ;;
184	(p1) cmp.eq p1, p2 = VRN_KERNEL, r30 ;;	184	(p1) cmp.eq p1, p2 = VRN_KERNEL, r30 ;;
185		185
186	/*	186	/*
187	* If BSPSTORE needs to be switched, p1 is false and p2 is true.	187	* If BSPSTORE needs to be switched, p1 is false and p2 is true.
188	*/	188	*/
189	(p1) mov r30 = r28	189	(p1) mov r30 = r28
190	(p2) mov r30 = R_KSTACK_BSP ;;	190	(p2) mov r30 = R_KSTACK_BSP ;;
191	(p2) mov ar.bspstore = r30 ;;	191	(p2) mov ar.bspstore = r30 ;;
192		192
193	mov r29 = ar.bsp	193	mov r29 = ar.bsp
194		194
195	st8 [r31] = r27, -8 ;; /* save ar.rnat */	195	st8 [r31] = r27, -8 ;; /* save ar.rnat */
196	st8 [r31] = r30, -8 ;; /* save new value written to ar.bspstore */	196	st8 [r31] = r30, -8 ;; /* save new value written to ar.bspstore */
197	st8 [r31] = r28, -8 ;; /* save ar.bspstore */	197	st8 [r31] = r28, -8 ;; /* save ar.bspstore */
198	st8 [r31] = r29, -8 /* save ar.bsp */	198	st8 [r31] = r29, -8 /* save ar.bsp */
199		199
200	mov ar.rsc = r24 /* restore RSE's setting + kernel privileges */	200	mov ar.rsc = r24 /* restore RSE's setting + kernel privileges */
201		201
202	/* steps 6 - 15 are done by heavyweight_handler_inner() */	202	/* steps 6 - 15 are done by heavyweight_handler_inner() */
203	mov R_RET = b0 /* save b0 belonging to interrupted context */	203	mov R_RET = b0 /* save b0 belonging to interrupted context */
204	br.call.sptk.many b0 = heavyweight_handler_inner	204	br.call.sptk.many b0 = heavyweight_handler_inner
205	0: mov b0 = R_RET /* restore b0 belonging to the interrupted context */	205	0: mov b0 = R_RET /* restore b0 belonging to the interrupted context */
206		206
207	/* 16. RSE switch to interrupted context */	207	/* 16. RSE switch to interrupted context */
208	cover /* allocate zerro size frame (step 1 (from Intel Docs)) */	208	cover /* allocate zerro size frame (step 1 (from Intel Docs)) */
209		209
210	add r31 = (STACK_SCRATCH_AREA_SIZE+(FRS_TO_SAVE28)), r12 ;;	210	add r31 = (STACK_SCRATCH_AREA_SIZE+(FRS_TO_SAVE28)), r12 ;;
211		211
212	ld8 r30 = [r31], +8 ;; /* load ar.bsp */	212	ld8 r30 = [r31], +8 ;; /* load ar.bsp */
213	ld8 r29 = [r31], +8 ;; /* load ar.bspstore */	213	ld8 r29 = [r31], +8 ;; /* load ar.bspstore */
214	ld8 r28 = [r31], +8 ;; /* load ar.bspstore_new */	214	ld8 r28 = [r31], +8 ;; /* load ar.bspstore_new */
215	sub r27 = r30 , r28 ;; /* calculate loadrs (step 2) */	215	sub r27 = r30 , r28 ;; /* calculate loadrs (step 2) */
216	shl r27 = r27, 16	216	shl r27 = r27, 16
217		217
218	mov r24 = ar.rsc ;;	218	mov r24 = ar.rsc ;;
219	and r30 = ~3, r24 ;;	219	and r30 = ~3, r24 ;;
220	or r24 = r30 , r27 ;;	220	or r24 = r30 , r27 ;;
221	mov ar.rsc = r24 ;; /* place RSE in enforced lazy mode */	221	mov ar.rsc = r24 ;; /* place RSE in enforced lazy mode */
222		222
223	loadrs /* (step 3) */	223	loadrs /* (step 3) */
224		224
225	ld8 r27 = [r31], +8 ;; /* load ar.rnat */	225	ld8 r27 = [r31], +8 ;; /* load ar.rnat */
226	ld8 r26 = [r31], +8 ;; /* load cr.ifs */	226	ld8 r26 = [r31], +8 ;; /* load cr.ifs */
227	ld8 r25 = [r31], +8 ;; /* load ar.pfs */	227	ld8 r25 = [r31], +8 ;; /* load ar.pfs */
228	ld8 r24 = [r31], +8 ;; /* load ar.rsc */	228	ld8 r24 = [r31], +8 ;; /* load ar.rsc */
229		229
230	mov ar.bspstore = r29 ;; /* (step 4) */	230	mov ar.bspstore = r29 ;; /* (step 4) */
231	mov ar.rnat = r27 /* (step 5) */	231	mov ar.rnat = r27 /* (step 5) */
232		232
233	mov ar.pfs = r25 /* (step 6) */	233	mov ar.pfs = r25 /* (step 6) */
234	mov cr.ifs = r26	234	mov cr.ifs = r26
235		235
236	mov ar.rsc = r24 /* (step 7) */	236	mov ar.rsc = r24 /* (step 7) */
237		237
238	/* 17. restore interruption state from memory stack */	238	/* 17. restore interruption state from memory stack */
239	ld8 r28 = [r31], +8 ;; /* load cr.ifa */	239	ld8 r28 = [r31], +8 ;; /* load cr.ifa */
240	ld8 r27 = [r31], +8 ;; /* load cr.isr */	240	ld8 r27 = [r31], +8 ;; /* load cr.isr */
241	ld8 r26 = [r31], +8 ;; /* load cr.iipa */	241	ld8 r26 = [r31], +8 ;; /* load cr.iipa */
242	ld8 r25 = [r31], +8 ;; /* load cr.ipsr */	242	ld8 r25 = [r31], +8 ;; /* load cr.ipsr */
243	ld8 r24 = [r31], +8 ;; /* load cr.iip */	243	ld8 r24 = [r31], +8 ;; /* load cr.iip */
244		244
245	mov cr.iip = r24;;	245	mov cr.iip = r24;;
246	mov cr.iipa = r26	246	mov cr.iipa = r26
247	mov cr.isr = r27	247	mov cr.isr = r27
248	mov cr.ifa = r28	248	mov cr.ifa = r28
249		249
250	/* Set up FPU as in exception. */	250	/* Set up FPU as in exception. */
251	mov r24 = psr	251	mov r24 = psr
252	mov r26 = PSR_DFH_MASK	252	mov r26 = PSR_DFH_MASK
253	mov r27 = ~PSR_DFH_MASK ;;	253	mov r27 = ~PSR_DFH_MASK ;;
254	and r25 = r25, r27	254	and r25 = r25, r27
255	and r24 = r24, r26 ;;	255	and r24 = r24, r26 ;;
256	or r25 = r25, r24;;	256	or r25 = r25, r24;;
257	mov cr.ipsr = r25	257	mov cr.ipsr = r25
258		258
259	/* 18. restore predicate registers from memory stack */	259	/* 18. restore predicate registers from memory stack */
260	ld8 r29 = [r31], +8 ;; /* load predicate registers */	260	ld8 r29 = [r31], +8 ;; /* load predicate registers */
261	mov pr = r29	261	mov pr = r29
262		262
263	/* 19. return from interruption */	263	/* 19. return from interruption */
264	ld8 r12 = [r31] /* load stack pointer */	264	ld8 r12 = [r31] /* load stack pointer */
265	rfi ;;	265	rfi ;;
266		266
267	.global heavyweight_handler_inner	267	.global heavyweight_handler_inner
268	heavyweight_handler_inner:	268	heavyweight_handler_inner:
269	/*	269	/*
270	* From this point, the rest of the interrupted context	270	* From this point, the rest of the interrupted context
271	* will be preserved in stacked registers and backing store.	271	* will be preserved in stacked registers and backing store.
272	*/	272	*/
273	alloc loc0 = ar.pfs, 0, 48, 2, 0 ;;	273	alloc loc0 = ar.pfs, 0, 48, 2, 0 ;;
274		274
275	/* bank 0 is going to be shadowed, copy essential data from there */	275	/* bank 0 is going to be shadowed, copy essential data from there */
276	mov loc1 = R_RET /* b0 belonging to interrupted context */	276	mov loc1 = R_RET /* b0 belonging to interrupted context */
277	mov loc2 = R_HANDLER	277	mov loc2 = R_HANDLER
278	mov out0 = R_OFFS	278	mov out0 = R_OFFS
279		279
280	add out1 = STACK_SCRATCH_AREA_SIZE, r12	280	add out1 = STACK_SCRATCH_AREA_SIZE, r12
281		281
282	/* 6. switch to bank 1 and reenable PSR.ic */	282	/* 6. switch to bank 1 and reenable PSR.ic */
283	ssm PSR_IC_MASK	283	ssm PSR_IC_MASK
284	bsw.1 ;;	284	bsw.1 ;;
285	srlz.d	285	srlz.d
286		286
287	/* 7. preserve branch and application registers */	287	/* 7. preserve branch and application registers */
288	mov loc3 = ar.unat	288	mov loc3 = ar.unat
289	mov loc4 = ar.lc	289	mov loc4 = ar.lc
290	mov loc5 = ar.ec	290	mov loc5 = ar.ec
291	mov loc6 = ar.ccv	291	mov loc6 = ar.ccv
292	mov loc7 = ar.csd	292	mov loc7 = ar.csd
293	mov loc8 = ar.ssd	293	mov loc8 = ar.ssd
294		294
295	mov loc9 = b0	295	mov loc9 = b0
296	mov loc10 = b1	296	mov loc10 = b1
297	mov loc11 = b2	297	mov loc11 = b2
298	mov loc12 = b3	298	mov loc12 = b3
299	mov loc13 = b4	299	mov loc13 = b4
300	mov loc14 = b5	300	mov loc14 = b5
301	mov loc15 = b6	301	mov loc15 = b6
302	mov loc16 = b7	302	mov loc16 = b7
303		303
304	/* 8. preserve general and floating-point registers */	304	/* 8. preserve general and floating-point registers */
305	mov loc17 = r1	305	mov loc17 = r1
306	mov loc18 = r2	306	mov loc18 = r2
307	mov loc19 = r3	307	mov loc19 = r3
308	mov loc20 = r4	308	mov loc20 = r4
309	mov loc21 = r5	309	mov loc21 = r5
310	mov loc22 = r6	310	mov loc22 = r6
311	mov loc23 = r7	311	mov loc23 = r7
312	(p5) mov loc24 = r8 /* only if not in break_instruction handler */	312	(p5) mov loc24 = r8 /* only if not in break_instruction handler */
313	mov loc25 = r9	313	mov loc25 = r9
314	mov loc26 = r10	314	mov loc26 = r10
315	mov loc27 = r11	315	mov loc27 = r11
316	/* skip r12 (stack pointer) */	316	/* skip r12 (stack pointer) */
317	mov loc28 = r13	317	mov loc28 = r13
318	mov loc29 = r14	318	mov loc29 = r14
319	mov loc30 = r15	319	mov loc30 = r15
320	mov loc31 = r16	320	mov loc31 = r16
321	mov loc32 = r17	321	mov loc32 = r17
322	mov loc33 = r18	322	mov loc33 = r18
323	mov loc34 = r19	323	mov loc34 = r19
324	mov loc35 = r20	324	mov loc35 = r20
325	mov loc36 = r21	325	mov loc36 = r21
326	mov loc37 = r22	326	mov loc37 = r22
327	mov loc38 = r23	327	mov loc38 = r23
328	mov loc39 = r24	328	mov loc39 = r24
329	mov loc40 = r25	329	mov loc40 = r25
330	mov loc41 = r26	330	mov loc41 = r26
331	mov loc42 = r27	331	mov loc42 = r27
332	mov loc43 = r28	332	mov loc43 = r28
333	mov loc44 = r29	333	mov loc44 = r29
334	mov loc45 = r30	334	mov loc45 = r30
335	mov loc46 = r31	335	mov loc46 = r31
336		336
337	add r24 = 96 + STACK_SCRATCH_AREA_SIZE, r12	337	add r24 = 96 + STACK_SCRATCH_AREA_SIZE, r12
338	add r25 = 112 + STACK_SCRATCH_AREA_SIZE, r12	338	add r25 = 112 + STACK_SCRATCH_AREA_SIZE, r12
339	add r26 = 0 + STACK_SCRATCH_AREA_SIZE, r12	339	add r26 = 0 + STACK_SCRATCH_AREA_SIZE, r12
340	add r27 = 16 + STACK_SCRATCH_AREA_SIZE, r12	340	add r27 = 16 + STACK_SCRATCH_AREA_SIZE, r12
341	add r28 = 32 + STACK_SCRATCH_AREA_SIZE, r12	341	add r28 = 32 + STACK_SCRATCH_AREA_SIZE, r12
342	add r29 = 48 + STACK_SCRATCH_AREA_SIZE, r12	342	add r29 = 48 + STACK_SCRATCH_AREA_SIZE, r12
343	add r30 = 64 + STACK_SCRATCH_AREA_SIZE, r12	343	add r30 = 64 + STACK_SCRATCH_AREA_SIZE, r12
344	add r31 = 80 + STACK_SCRATCH_AREA_SIZE, r12 ;;	344	add r31 = 80 + STACK_SCRATCH_AREA_SIZE, r12 ;;
345		345
346	stf.spill [r26] = f2, 0x80	346	stf.spill [r26] = f2, 0x80
347	stf.spill [r27] = f3, 0x80	347	stf.spill [r27] = f3, 0x80
348	stf.spill [r28] = f4, 0x80	348	stf.spill [r28] = f4, 0x80
349	stf.spill [r29] = f5, 0x80	349	stf.spill [r29] = f5, 0x80
350	stf.spill [r30] = f6, 0x80	350	stf.spill [r30] = f6, 0x80
351	stf.spill [r31] = f7, 0x80 ;;	351	stf.spill [r31] = f7, 0x80 ;;
352		352
353	stf.spill [r24] = f8, 0x80	353	stf.spill [r24] = f8, 0x80
354	stf.spill [r25] = f9, 0x80	354	stf.spill [r25] = f9, 0x80
355	stf.spill [r26] = f10, 0x80	355	stf.spill [r26] = f10, 0x80
356	stf.spill [r27] = f11, 0x80	356	stf.spill [r27] = f11, 0x80
357	stf.spill [r28] = f12, 0x80	357	stf.spill [r28] = f12, 0x80
358	stf.spill [r29] = f13, 0x80	358	stf.spill [r29] = f13, 0x80
359	stf.spill [r30] = f14, 0x80	359	stf.spill [r30] = f14, 0x80
360	stf.spill [r31] = f15, 0x80 ;;	360	stf.spill [r31] = f15, 0x80 ;;
361		361
362	stf.spill [r24] = f16, 0x80	362	stf.spill [r24] = f16, 0x80
363	stf.spill [r25] = f17, 0x80	363	stf.spill [r25] = f17, 0x80
364	stf.spill [r26] = f18, 0x80	364	stf.spill [r26] = f18, 0x80
365	stf.spill [r27] = f19, 0x80	365	stf.spill [r27] = f19, 0x80
366	stf.spill [r28] = f20, 0x80	366	stf.spill [r28] = f20, 0x80
367	stf.spill [r29] = f21, 0x80	367	stf.spill [r29] = f21, 0x80
368	stf.spill [r30] = f22, 0x80	368	stf.spill [r30] = f22, 0x80
369	stf.spill [r31] = f23, 0x80 ;;	369	stf.spill [r31] = f23, 0x80 ;;
370		370
371	stf.spill [r24] = f24, 0x80	371	stf.spill [r24] = f24, 0x80
372	stf.spill [r25] = f25, 0x80	372	stf.spill [r25] = f25, 0x80
373	stf.spill [r26] = f26, 0x80	373	stf.spill [r26] = f26, 0x80
374	stf.spill [r27] = f27, 0x80	374	stf.spill [r27] = f27, 0x80
375	stf.spill [r28] = f28, 0x80	375	stf.spill [r28] = f28, 0x80
376	stf.spill [r29] = f29, 0x80	376	stf.spill [r29] = f29, 0x80
377	stf.spill [r30] = f30, 0x80	377	stf.spill [r30] = f30, 0x80
378	stf.spill [r31] = f31, 0x80 ;;	378	stf.spill [r31] = f31, 0x80 ;;
379		379
380	mov loc47 = ar.fpsr /* preserve floating point status register */	380	mov loc47 = ar.fpsr /* preserve floating point status register */
381		381
382	/* 9. skipped (will not enable interrupts) */	382	/* 9. skipped (will not enable interrupts) */
383	/*	383	/*
384	* ssm PSR_I_MASK	384	* ssm PSR_I_MASK
385	* ;;	385	* ;;
386	* srlz.d	386	* srlz.d
387	*/	387	*/
388		388
389	/* 10. call handler */	389	/* 10. call handler */
390	movl r1 = _hardcoded_load_address	390	movl r1 = _hardcoded_load_address
391		391
392	mov b1 = loc2	392	mov b1 = loc2
393	br.call.sptk.many b0 = b1	393	br.call.sptk.many b0 = b1
394		394
395	/* 11. return from handler */	395	/* 11. return from handler */
396	0:	396	0:
397		397
398	/* 12. skipped (will not disable interrupts) */	398	/* 12. skipped (will not disable interrupts) */
399	/*	399	/*
400	* rsm PSR_I_MASK	400	* rsm PSR_I_MASK
401	* ;;	401	* ;;
402	* srlz.d	402	* srlz.d
403	*/	403	*/
404		404
405	/* 13. restore general and floating-point registers */	405	/* 13. restore general and floating-point registers */
406	add r24 = 96 + STACK_SCRATCH_AREA_SIZE, r12	406	add r24 = 96 + STACK_SCRATCH_AREA_SIZE, r12
407	add r25 = 112 + STACK_SCRATCH_AREA_SIZE, r12	407	add r25 = 112 + STACK_SCRATCH_AREA_SIZE, r12
408	add r26 = 0 + STACK_SCRATCH_AREA_SIZE, r12	408	add r26 = 0 + STACK_SCRATCH_AREA_SIZE, r12
409	add r27 = 16 + STACK_SCRATCH_AREA_SIZE, r12	409	add r27 = 16 + STACK_SCRATCH_AREA_SIZE, r12
410	add r28 = 32 + STACK_SCRATCH_AREA_SIZE, r12	410	add r28 = 32 + STACK_SCRATCH_AREA_SIZE, r12
411	add r29 = 48 + STACK_SCRATCH_AREA_SIZE, r12	411	add r29 = 48 + STACK_SCRATCH_AREA_SIZE, r12
412	add r30 = 64 + STACK_SCRATCH_AREA_SIZE, r12	412	add r30 = 64 + STACK_SCRATCH_AREA_SIZE, r12
413	add r31 = 80 + STACK_SCRATCH_AREA_SIZE, r12 ;;	413	add r31 = 80 + STACK_SCRATCH_AREA_SIZE, r12 ;;
414		414
415	ldf.fill f2 = [r26], 0x80	415	ldf.fill f2 = [r26], 0x80
416	ldf.fill f3 = [r27], 0x80	416	ldf.fill f3 = [r27], 0x80
417	ldf.fill f4 = [r28], 0x80	417	ldf.fill f4 = [r28], 0x80
418	ldf.fill f5 = [r29], 0x80	418	ldf.fill f5 = [r29], 0x80
419	ldf.fill f6 = [r30], 0x80	419	ldf.fill f6 = [r30], 0x80
420	ldf.fill f7 = [r31], 0x80 ;;	420	ldf.fill f7 = [r31], 0x80 ;;
421		421
422	ldf.fill f8 = [r24], 0x80	422	ldf.fill f8 = [r24], 0x80
423	ldf.fill f9 = [r25], 0x80	423	ldf.fill f9 = [r25], 0x80
424	ldf.fill f10 = [r26], 0x80	424	ldf.fill f10 = [r26], 0x80
425	ldf.fill f11 = [r27], 0x80	425	ldf.fill f11 = [r27], 0x80
426	ldf.fill f12 = [r28], 0x80	426	ldf.fill f12 = [r28], 0x80
427	ldf.fill f13 = [r29], 0x80	427	ldf.fill f13 = [r29], 0x80
428	ldf.fill f14 = [r30], 0x80	428	ldf.fill f14 = [r30], 0x80
429	ldf.fill f15 = [r31], 0x80 ;;	429	ldf.fill f15 = [r31], 0x80 ;;
430		430
431	ldf.fill f16 = [r24], 0x80	431	ldf.fill f16 = [r24], 0x80
432	ldf.fill f17 = [r25], 0x80	432	ldf.fill f17 = [r25], 0x80
433	ldf.fill f18 = [r26], 0x80	433	ldf.fill f18 = [r26], 0x80
434	ldf.fill f19 = [r27], 0x80	434	ldf.fill f19 = [r27], 0x80
435	ldf.fill f20 = [r28], 0x80	435	ldf.fill f20 = [r28], 0x80
436	ldf.fill f21 = [r29], 0x80	436	ldf.fill f21 = [r29], 0x80
437	ldf.fill f22 = [r30], 0x80	437	ldf.fill f22 = [r30], 0x80
438	ldf.fill f23 = [r31], 0x80 ;;	438	ldf.fill f23 = [r31], 0x80 ;;
439		439
440	ldf.fill f24 = [r24], 0x80	440	ldf.fill f24 = [r24], 0x80
441	ldf.fill f25 = [r25], 0x80	441	ldf.fill f25 = [r25], 0x80
442	ldf.fill f26 = [r26], 0x80	442	ldf.fill f26 = [r26], 0x80
443	ldf.fill f27 = [r27], 0x80	443	ldf.fill f27 = [r27], 0x80
444	ldf.fill f28 = [r28], 0x80	444	ldf.fill f28 = [r28], 0x80
445	ldf.fill f29 = [r29], 0x80	445	ldf.fill f29 = [r29], 0x80
446	ldf.fill f30 = [r30], 0x80	446	ldf.fill f30 = [r30], 0x80
447	ldf.fill f31 = [r31], 0x80 ;;	447	ldf.fill f31 = [r31], 0x80 ;;
448		448
449	mov r1 = loc17	449	mov r1 = loc17
450	mov r2 = loc18	450	mov r2 = loc18
451	mov r3 = loc19	451	mov r3 = loc19
452	mov r4 = loc20	452	mov r4 = loc20
453	mov r5 = loc21	453	mov r5 = loc21
454	mov r6 = loc22	454	mov r6 = loc22
455	mov r7 = loc23	455	mov r7 = loc23
456	(p5) mov r8 = loc24 /* only if not in break_instruction handler */	456	(p5) mov r8 = loc24 /* only if not in break_instruction handler */
457	mov r9 = loc25	457	mov r9 = loc25
458	mov r10 = loc26	458	mov r10 = loc26
459	mov r11 = loc27	459	mov r11 = loc27
460	/* skip r12 (stack pointer) */	460	/* skip r12 (stack pointer) */
461	mov r13 = loc28	461	mov r13 = loc28
462	mov r14 = loc29	462	mov r14 = loc29
463	mov r15 = loc30	463	mov r15 = loc30
464	mov r16 = loc31	464	mov r16 = loc31
465	mov r17 = loc32	465	mov r17 = loc32
466	mov r18 = loc33	466	mov r18 = loc33
467	mov r19 = loc34	467	mov r19 = loc34
468	mov r20 = loc35	468	mov r20 = loc35
469	mov r21 = loc36	469	mov r21 = loc36
470	mov r22 = loc37	470	mov r22 = loc37
471	mov r23 = loc38	471	mov r23 = loc38
472	mov r24 = loc39	472	mov r24 = loc39
473	mov r25 = loc40	473	mov r25 = loc40
474	mov r26 = loc41	474	mov r26 = loc41
475	mov r27 = loc42	475	mov r27 = loc42
476	mov r28 = loc43	476	mov r28 = loc43
477	mov r29 = loc44	477	mov r29 = loc44
478	mov r30 = loc45	478	mov r30 = loc45
479	mov r31 = loc46	479	mov r31 = loc46
480		480
481	mov ar.fpsr = loc47 /* restore floating point status register */	481	mov ar.fpsr = loc47 /* restore floating point status register */
482		482
483	/* 14. restore branch and application registers */	483	/* 14. restore branch and application registers */
484	mov ar.unat = loc3	484	mov ar.unat = loc3
485	mov ar.lc = loc4	485	mov ar.lc = loc4
486	mov ar.ec = loc5	486	mov ar.ec = loc5
487	mov ar.ccv = loc6	487	mov ar.ccv = loc6
488	mov ar.csd = loc7	488	mov ar.csd = loc7
489	mov ar.ssd = loc8	489	mov ar.ssd = loc8
490		490
491	mov b0 = loc9	491	mov b0 = loc9
492	mov b1 = loc10	492	mov b1 = loc10
493	mov b2 = loc11	493	mov b2 = loc11
494	mov b3 = loc12	494	mov b3 = loc12
495	mov b4 = loc13	495	mov b4 = loc13
496	mov b5 = loc14	496	mov b5 = loc14
497	mov b6 = loc15	497	mov b6 = loc15
498	mov b7 = loc16	498	mov b7 = loc16
499		499
500	/* 15. disable PSR.ic and switch to bank 0 */	500	/* 15. disable PSR.ic and switch to bank 0 */

Subversion Repositories HelenOS

(root)/trunk/kernel/arch/ia64/src/ivt.S – Rev 1787 → 2071